US5800725A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor wafers
Assignee: Shin-Etsu Handotai Co Ltd
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Filing: 1997-01-28
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Granted: 1998-09-01
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Expires: 2017-01-28
Abstract
Abstract A method of manufacturing semiconductor wafers includes a double side primary polishing step, a back side etching step and a single side mirror polishing step. This method is capable of easy sensor detection of the front and back sides of the wafer, wafer processing of higher flatness level by forming etched rough surface at the back side of the double side polished wafer and setting up of wafer manufacturing process including a double side polishing step.
Inventors
- 👤 Tadahiro Kato
- 👤 Hisashi Masumura
- 👤 Hideo Kudo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:20
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/12
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
58 words
A method of manufacturing semiconductor wafers which comprises the steps of: (a) double side primary polishing of both the front and back sides of a starting wafer; (b) back side etching of the back side alone of the double side polished wafer; and (c) single side mirror polishing of the front side of the back side etched wafer.
Claim 2
Independent Claim
58 words
A method of manufacturing semiconductor wafers which comprises the steps of: (a) double side primary polishing of both the front and back sides of a starting wafer; (b) back side etching of the back side alone of the double side polished wafer; and (c) single side mirror polishing of the front side of the back side etched wafer.
Claim 3
Dependent Claim
30 words
A method of manufacturing semiconductor wafers according to claim 1, wherein an etched wafer which was subjected to etching treatment to remove processing damage is used as the starting wafer.
Claim 4
Dependent Claim
33 words
A method of manufacturing semiconductor wafers according to claim 1, wherein the single side mirror polishing step includes a single side secondary mirror polishing step and a single side final mirror polishing step.
Claim 5
Dependent Claim
33 words
A method of manufacturing semiconductor wafers according to claim 2, wherein the single side mirror polishing step includes a single side secondary mirror polishing step and a single side final mirror polishing step.
Claim 6
Dependent Claim
23 words
A method of manufacturing semiconductor wafers according to claim 1, wherein an acid etching step is used for the back side etching step.
Claim 7
Dependent Claim
23 words
A method of manufacturing semiconductor wafers according to claim 2, wherein an acid etching step is used for the back side etching step.
Claim 8
Dependent Claim
23 words
A method of manufacturing semiconductor wafers according to claim 3, wherein an acid etching step is used for the back side etching step.
Claim 9
Dependent Claim
32 words
A method of manufacturing semiconductor wafers according to claim 5, wherein the acid etching step is conducted with an acid etching solution containing hydrofluoric acid, nitric acid, sulfuric acid and water indispensably.
Claim 10
Dependent Claim
32 words
A method of manufacturing semiconductor wafers according to claim 6, wherein the acid etching step is conducted with an acid etching solution containing hydrofluoric acid, nitric acid, sulfuric acid and water indispensably.
Claim 11
Dependent Claim
32 words
A method of manufacturing semiconductor wafers according to claim 7, wherein the acid etching step is conducted with an acid etching solution containing hydrofluoric acid, nitric acid, sulfuric acid and water indispensably.
Claim 12
Dependent Claim
22 words
A method of manufacturing semiconductor wafers according to claim 8, wherein the acid etching solution further contains acetic acid and/or phosphoric acid.
Claim 13
Dependent Claim
22 words
A method of manufacturing semiconductor wafers according to claim 9, wherein the acid etching solution further contains acetic acid and/or phosphoric acid.
Claim 14
Dependent Claim
22 words
A method of manufacturing semiconductor wafers according to claim 10, wherein the acid etching solution further contains acetic acid and/or phosphoric acid.
References Cited (Backward Citations)
US5071776A
Cited
JPH03211718A
Cited
JPH04124823A
Cited
US5424224A
Cited
JPH0745564A
Cited
JPH08316180A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |