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US5798723A
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Accurate and precise current matching for low voltage CMOS digital to analog converters
Assignee: National Semiconductor Corp
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Filing: 1996-07-19
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Granted: 1998-08-25
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Expires: 2016-07-19
Abstract
Abstract An operational amplifier in a bias voltage generator of a MOS current summing digital to analog converter corrects deviations in output current due to variations in drain to source voltages in current slaves caused by differing output resistances and supply voltages. Matching of MOS current sources uses an operational amplifier feedback circuit to create a controlled turn-on reference voltage used for biasing selected differential current paths so as to eliminate drain to source voltage variations in precisely ratioed current slave MOS transistors. One transistor of each differential current pair is enabled by a corresponding switch coupled to the turn-on reference voltage produced by the operational amplifier. In the preferred embodiment, the switches are CMOS transmission gates enabled by the binary digital input and its complement. Low voltage (3 volts) operation is achieved by having minimum number of stacked transistors between power supply voltages. Reliable current matching allows converter resolution of 10 bits. Due to cascode switching action controlling alternative differential current paths, output current is independent of output resistance. The operational amplifier samples the current bias reference used to bias the binary ratioed slaves and the drain of a current mirror and drives a feedback transistor gate and the enabled differential current paths with the turn-on reference voltage so that the precisely ratioed current slaves have the same drain to source voltage as the reference current transistor. The reference voltages produced are thereby independent of supply voltages and process.
Inventors
- 👤 Edison Fong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:01
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0602; H03M1/0604; H03M1/66; H03M1/74; H03M1/742
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
164 words
A MOS current-summing digital-to-analog converter bias voltage generator having a current bias reference output and a turnon reference output, the generator comprising: a reference current transistor of a first conductivity type having a reference current source, a reference current gate, and a reference current drain; a current mirror transistor of the first conductivity type having a current mirror source, a current mirror gate, and a current mirror drain; an operational amplifier having a plus input, a minus input, and an operational amplifier output; and a feedback transistor of the first conductivity type having a feedback source, a feedback gate, and a feedback drain; wherein the operational amplifier plus input is coupled to the current mirror gate, and the reference current gate and drain, and the current bias reference output; and wherein the feedback gate is coupled to the operational amplifier output and the turnon reference output, and wherein the feedback source is coupled to the operational amplifier minus input and the current mirror drain.
Claim 2
Dependent Claim
164 words
A MOS current-summing digital-to-analog converter bias voltage generator having a current bias reference output and a turnon reference output, the generator comprising: a reference current transistor of a first conductivity type having a reference current source, a reference current gate, and a reference current drain; a current mirror transistor of the first conductivity type having a current mirror source, a current mirror gate, and a current mirror drain; an operational amplifier having a plus input, a minus input, and an operational amplifier output; and a feedback transistor of the first conductivity type having a feedback source, a feedback gate, and a feedback drain; wherein the operational amplifier plus input is coupled to the current mirror gate, and the reference current gate and drain, and the current bias reference output; and wherein the feedback gate is coupled to the operational amplifier output and the turnon reference output, and wherein the feedback source is coupled to the operational amplifier minus input and the current mirror drain.
Claim 3
Dependent Claim
62 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 1, further comprising: a generator bias transistor of a second conductivity type having a generator bias drain, a generator bias source, and a generator bias gate; wherein the generator bias drain is coupled to the operational amplifier plus input, and the generator bias gate is coupled to an input reference voltage.
Claim 4
Dependent Claim
59 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 2, further comprising: a current mirror sink transistor of the second conductivity type having a current mirror sink gate, a current mirror sink drain, and a current mirror sink source, wherein the current mirror sink drain is coupled to the current mirror sink gate and the feedback drain.
Claim 5
Dependent Claim
28 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 2, wherein the first conductivity type is p-channel MOS and the second conductivity type is n-channel MOS.
Claim 6
Dependent Claim
65 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 4, further comprising: a pnp bipolar current mirror sink transistor having a current mirror sink base, a current mirror sink collector, and a current mirror sink emitter; and wherein the current mirror sink emitter is coupled to the feedback drain, and the current mirror sink collector is coupled to the current mirror sink gate.
Claim 7
Dependent Claim
31 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 5, wherein a ground voltage is coupled to the generator bias source and the current mirror sink base and collector.
Claim 8
Dependent Claim
29 words
A MOS current-summing digital-to-analog converter bias voltage generator as in claim 5, wherein a positive supply voltage is coupled to the reference current source and the current mirror source.
Claim 9
Dependent Claim
704 words
A MOS current-summing digital-to-analog converter circuit having first and second non-inverting and inverting binary weighted digital inputs and non-inverting and inverting analog output voltages, comprising: a reference current transistor of a first conductivity type having a reference current source, a reference current gate, and a reference current drain; a current mirror transistor of the first conductivity type having a current mirror source, a current mirror gate, and a current mirror drain; an operational amplifier having a plus input, a minus input, and an operational amplifier output; a feedback transistor of the first conductivity type having a feedback source, a feedback gate, and a feedback drain; a first weighted-current slave transistor of the first conductivity type having a first channel W/L ratio having a first weighted-current slave source, a first weighted-current slave gate, and a first weighted-current slave drain; a second weighted-current slave transistor of the first conductivity type having a second channel W/L ratio having a second weighted-current slave source, a second weighted-current slave gate, and a second weighted-current slave drain, wherein the second W/L ratio divided by the first W/L ratio is a radix factor not equal to one; a first non-inverting differential transistor of the first conductivity type having a first non-inverting differential source, a first non-inverting differential gate, and a first non-inverting differential drain; a first inverting differential transistor of the first conductivity type having a first inverting differential source, a first inverting differential gate, and a first inverting differential drain; a second non-inverting differential transistor of the first conductivity type having a second non-inverting differential source, a second non-inverting differential gate, and a second non-inverting differential drain; a second inverting differential transistor of the first conductivity type having a second inverting differential source, a second inverting differential gate, and a second inverting differential drain; a first non-inverting control transistor of a second conductivity type having a first non-inverting control source, a first non-inverting control gate, and a first non-inverting control drain; a first inverting control transistor of the second conductivity type having a first inverting control source, a first inverting control gate, and a first inverting control drain; a second non-inverting control transistor of the second conductivity type having a second non-inverting control source, a second non-inverting control gate, and a second non-inverting control drain; and a second inverting control transistor of the second conductivity type having a second inverting control source, a second inverting control gate, and a second inverting control drain; wherein the first non-inverting control drain is coupled to the first non-inverting differential gate, wherein the first non-inverting control gate is coupled to the first non-inverting weighted binary digital input, and wherein the first non-inverting control source is coupled to the operational amplifier output; wherein the first inverting control drain is coupled to the first inverting differential gate, wherein the first inverting control gate is coupled to the first inverting weighted binary digital input, and wherein the first inverting control source is coupled to the operational amplifier output; wherein the second non-inverting control drain is coupled to the second non-inverting differential gate, wherein the second non-inverting control gate is coupled to the second non-inverting weighted binary digital input, and wherein the second non-inverting control source is coupled to the operational amplifier output; wherein the second inverting control drain is coupled to the second inverting differential gate, wherein the second inverting control gate is coupled to the second inverting weighted binary digital input, and wherein the second inverting control source is coupled to the operational amplifier output; wherein the first and second non-inverting differential drains are coupled to the non-inverting analog output voltage; wherein the first and second inverting differential drains are coupled to the inverting analog output voltage; wherein the first non-inverting and inverting differential sources are coupled to the first weighted-current slave drain; wherein the second non-inverting and inverting differential sources are coupled to the second weighted-current slave drain; wherein the operational amplifier plus input is coupled to the first and second weighted-current slave gates, the current mirror gate, and the reference current gate and drain; and wherein the feedback gate is coupled to the operational amplifier output, and wherein the feedback source is coupled to the operational amplifier minus input and the current mirror drain.
Claim 10
Dependent Claim
704 words
A MOS current-summing digital-to-analog converter circuit having first and second non-inverting and inverting binary weighted digital inputs and non-inverting and inverting analog output voltages, comprising: a reference current transistor of a first conductivity type having a reference current source, a reference current gate, and a reference current drain; a current mirror transistor of the first conductivity type having a current mirror source, a current mirror gate, and a current mirror drain; an operational amplifier having a plus input, a minus input, and an operational amplifier output; a feedback transistor of the first conductivity type having a feedback source, a feedback gate, and a feedback drain; a first weighted-current slave transistor of the first conductivity type having a first channel W/L ratio having a first weighted-current slave source, a first weighted-current slave gate, and a first weighted-current slave drain; a second weighted-current slave transistor of the first conductivity type having a second channel W/L ratio having a second weighted-current slave source, a second weighted-current slave gate, and a second weighted-current slave drain, wherein the second W/L ratio divided by the first W/L ratio is a radix factor not equal to one; a first non-inverting differential transistor of the first conductivity type having a first non-inverting differential source, a first non-inverting differential gate, and a first non-inverting differential drain; a first inverting differential transistor of the first conductivity type having a first inverting differential source, a first inverting differential gate, and a first inverting differential drain; a second non-inverting differential transistor of the first conductivity type having a second non-inverting differential source, a second non-inverting differential gate, and a second non-inverting differential drain; a second inverting differential transistor of the first conductivity type having a second inverting differential source, a second inverting differential gate, and a second inverting differential drain; a first non-inverting control transistor of a second conductivity type having a first non-inverting control source, a first non-inverting control gate, and a first non-inverting control drain; a first inverting control transistor of the second conductivity type having a first inverting control source, a first inverting control gate, and a first inverting control drain; a second non-inverting control transistor of the second conductivity type having a second non-inverting control source, a second non-inverting control gate, and a second non-inverting control drain; and a second inverting control transistor of the second conductivity type having a second inverting control source, a second inverting control gate, and a second inverting control drain; wherein the first non-inverting control drain is coupled to the first non-inverting differential gate, wherein the first non-inverting control gate is coupled to the first non-inverting weighted binary digital input, and wherein the first non-inverting control source is coupled to the operational amplifier output; wherein the first inverting control drain is coupled to the first inverting differential gate, wherein the first inverting control gate is coupled to the first inverting weighted binary digital input, and wherein the first inverting control source is coupled to the operational amplifier output; wherein the second non-inverting control drain is coupled to the second non-inverting differential gate, wherein the second non-inverting control gate is coupled to the second non-inverting weighted binary digital input, and wherein the second non-inverting control source is coupled to the operational amplifier output; wherein the second inverting control drain is coupled to the second inverting differential gate, wherein the second inverting control gate is coupled to the second inverting weighted binary digital input, and wherein the second inverting control source is coupled to the operational amplifier output; wherein the first and second non-inverting differential drains are coupled to the non-inverting analog output voltage; wherein the first and second inverting differential drains are coupled to the inverting analog output voltage; wherein the first non-inverting and inverting differential sources are coupled to the first weighted-current slave drain; wherein the second non-inverting and inverting differential sources are coupled to the second weighted-current slave drain; wherein the operational amplifier plus input is coupled to the first and second weighted-current slave gates, the current mirror gate, and the reference current gate and drain; and wherein the feedback gate is coupled to the operational amplifier output, and wherein the feedback source is coupled to the operational amplifier minus input and the current mirror drain.
Claim 11
Dependent Claim
35 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, further comprising: a constant current source having an input and output, wherein the constant current source input is coupled to the operational amplifier plus input.
Claim 12
Dependent Claim
242 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, further comprising: a first non-inverting turnoff transistor of the first conductivity type having a first non-inverting turnoff source, a first non-inverting turnoff gate, and a first non-inverting turnoff drain; a first inverting turnoff transistor of the first conductivity type having a first inverting turnoff source, a first inverting turnoff gate, and a first inverting turnoff drain; a second non-inverting turnoff transistor of the first conductivity type having a second non-inverting turnoff source, a second non-inverting turnoff gate, and a second non-inverting turnoff drain; and a second inverting turnoff transistor of the first conductivity type having a second inverting turnoff source, a second inverting turnoff gate, and a second inverting turnoff drain; wherein the first non-inverting turnoff gate is coupled to the first non-inverting binary weighted digital input, wherein the first non-inverting turnoff drain is coupled to the first non-inverting differential gate; wherein the first inverting turnoff gate is coupled to the first inverting binary weighted digital input, wherein the first inverting turnoff drain is coupled to the first inverting differential gate; wherein the second non-inverting turnoff gate is coupled to the second non-inverting binary weighted digital input, wherein the second non-inverting turnoff drain is coupled to the second non-inverting differential gate; and wherein the second inverting turnoff gate is coupled to the second inverting binary weighted digital input, wherein the second inverting turnoff drain is coupled to the second inverting differential gate.
Claim 13
Dependent Claim
57 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, further comprising: a current mirror sink transistor of the second conductivity type having a current mirror sink gate, a current mirror sink drain, and a current mirror sink source, wherein the current mirror sink drain is coupled to the current mirror sink gate and the feedback drain.
Claim 14
Dependent Claim
48 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, further comprising: a non-inverting output resistor; and an inverting output resistor; wherein the non-inverting output resistor is coupled to the non-inverting analog output voltage; and wherein the inverting output resistor is coupled to the inverting analog output voltage.
Claim 15
Dependent Claim
26 words
A MOS current-summing digital-to-analog converter circuit as in claim 10, wherein the first conductivity type is p-channel MOS and the second conductivity type is n-channel MOS.
Claim 16
Dependent Claim
43 words
A MOS current-summing digital-to-analog converter circuit as in claim 13, wherein a positive supply voltage is coupled to the reference current source, the current mirror source, the first and second weighted-current slave sources, and the first and second non-inverting and inverting turnoff sources.
Claim 17
Dependent Claim
26 words
A MOS current-summing digital-to-analog converter circuit as in claim 10, wherein the first conductivity type is n-channel MOS and the second conductivity type is p-channel MOS.
Claim 18
Dependent Claim
42 words
A MOS current-summing digital-to-analog converter circuit as in claim 15, wherein a ground voltage is coupled to the reference current source, the current mirror source, the first and second weighted-current slave sources, and the first and second non-inverting and inverting turnoff sources.
Claim 19
Dependent Claim
58 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, wherein the first inverting and non-inverting differential transistors have a first differential W/L parameter; wherein the second inverting and non-inverting differential transistors have a second differential W/L parameter; such that the second differential W/L parameter divided by the first differential W/L parameter is equal to the radix factor.
Claim 20
Dependent Claim
16 words
A MOS current-summing digital-to-analog converter circuit as in claim 8, wherein the radix factor is 2.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |