Abstract An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode. The control circuit has a first mode which disables the first and second p-channel transistors and enables the first n-channel transistor for operation with a first voltage supply level present at the voltage supply node and which the enables the second inverter stage and which turns the third n-channel transistor off.
An input/output buffer, comprising: a bidirectional node; an output stage having a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node; an input stage having a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node, the input stage having a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node; and a control circuit, coupled to the output stage and to the input stage, which enables the output stage when in an output mode and which disables the output stage when in an input mode, the control circuit having a first mode which disables the first and second p-channel transistors and enables the first n-channel transistor for operation with a first voltage supply level present at the voltage supply node and which the enables the second inverter stage and which turns the third n-channel transistor off.
Claim 2
Dependent Claim
203 words
An input/output buffer, comprising: a bidirectional node; an output stage having a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node; an input stage having a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node, the input stage having a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node; and a control circuit, coupled to the output stage and to the input stage, which enables the output stage when in an output mode and which disables the output stage when in an input mode, the control circuit having a first mode which disables the first and second p-channel transistors and enables the first n-channel transistor for operation with a first voltage supply level present at the voltage supply node and which the enables the second inverter stage and which turns the third n-channel transistor off.
Claim 3
Dependent Claim
34 words
A buffer circuit in accordance with claim 1, further comprising: a voltage regulator coupled to a gate of the first n-channel transistor and to the control circuit for turning the first n-channel transistor on.
Claim 4
Dependent Claim
47 words
A buffer circuit in accordance with claim 1, further comprising: a delay circuit coupled to a gate of the second p-channel transistor and to the control circuit for turning the second p-channel transistor on a delay time period subsequent to the first p-channel transistor being turned on.
Claim 5
Dependent Claim
31 words
A buffer circuit in accordance with claim 1, further comprising: a NOR gate having one input coupled to the first intermediate node and another input coupled to the second intermediate node.