Patent US5796650A successfully refreshed from Google Patents.
US5796650A
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Memory circuit including write control unit wherein subthreshold leakage may be reduced
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1997-05-19
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Granted: 1998-08-18
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Expires: 2017-05-19
Abstract
Abstract A memory circuit wherein subthreshold leakage current may be reduced. The memory circuit includes a memory array composed of one or more storage cells that are each configured to store a memory value on a storage transistor. The storage cells further include a write transistor coupled to the storage transistor that is configured to allow data driven on a write bit line to be stored to the storage transistor. The write bit line is coupled to a write control unit, which includes a buffer and a offset voltage element. The buffer is configured to establish an output voltage on the write bit line in response to an input voltage. The offset voltage element is coupled to the buffer, and is configured to offset the output voltage on the write bit line by a predetermined amount. In one implementation of the write control unit, the buffer is formed by an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a diode-connected transistor coupled between the inverter and ground. The diode-connected transistor has the effect of holding the write bit line at a level equal to its threshold voltage when the n-channel transistor of the inverter is active. In another implementation, the buffer is also an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a pullup transistor that is active when the n-channel transitor of the inverter is active. The pullup transistor forms a voltage divider with the n-channel transistor, such that the voltage between the write bit line and ground is offset by an amount determined by the voltage drop across the pullup transistor. The offset voltage established by the write control unit biases the write transistor such that subthreshold leakage current may be reduced when the write transistor is off.
Inventors
- 👤 Thomas R. Wik
- 👤 Shahryar Aryani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
170 words
A memory circuit comprising: a memory array including at least one storage cell configured to store a memory value on a storage node formed by a capacitance coupled to said storage node, wherein said at least one storage cell includes a write transistor configured to cause write data driven on a write bit line to be written to said storage node; and a write control unit coupled to said write bit line and a first reference voltage, wherein said write control unit includes: a buffer coupled to said write bit line, wherein said buffer is configured to convey a first output voltage on said write bit line in response to a first input voltage, and wherein said first output voltage establishes a first output logic state; and an offset voltage element coupled to said buffer, wherein said offset voltage element is configured to cause said first output voltage to be offset from said first reference voltage by an amount determined by an offset voltage established across said offset voltage element.
Claim 2
Dependent Claim
170 words
A memory circuit comprising: a memory array including at least one storage cell configured to store a memory value on a storage node formed by a capacitance coupled to said storage node, wherein said at least one storage cell includes a write transistor configured to cause write data driven on a write bit line to be written to said storage node; and a write control unit coupled to said write bit line and a first reference voltage, wherein said write control unit includes: a buffer coupled to said write bit line, wherein said buffer is configured to convey a first output voltage on said write bit line in response to a first input voltage, and wherein said first output voltage establishes a first output logic state; and an offset voltage element coupled to said buffer, wherein said offset voltage element is configured to cause said first output voltage to be offset from said first reference voltage by an amount determined by an offset voltage established across said offset voltage element.
Claim 3
Dependent Claim
55 words
The memory circuit as recited in claim 1 wherein said buffer is coupled to a second reference voltage, and wherein said buffer is further configured to convey a second output voltage on said write bit line in response to a second input voltage, and wherein said second output voltage establishes a second output logic state.
Claim 4
Dependent Claim
52 words
The memory circuit as recited in claim 2 wherein said buffer includes a first transistor and a second transistor, wherein said first transistor is configured to turn on in response to said first input voltage, and wherein said second transistor is configured to turn on in response to said second input voltage.
Claim 5
Dependent Claim
18 words
The memory circuit as recited in claim 1 wherein said storage node is formed by a storage transistor.
Claim 6
Dependent Claim
27 words
The memory circuit as recited in claim 4 wherein said capacitance is formed between a gate of said storage transistor and a source of said storage transistor.
Claim 7
Dependent Claim
31 words
The memory circuit as recited in claim 5 wherein said first output voltage is offset from said first reference voltage by approximately a threshold voltage level associated with said storage transistor.
Claim 8
Dependent Claim
18 words
The memory circuit as recited in claim 1 further includes an address decoder coupled to said memory array.
Claim 9
Dependent Claim
36 words
The memory circuit as recited in claim 1 wherein a source of said write transistor and a drain of said write transistor are coupled between said write bit line and said gate of said storage transistor.
Claim 10
Dependent Claim
37 words
The memory circuit as recited in claim 8 further includes a write word line coupled to a gate of said write transistor, wherein said write word line is configured to turn on and off said write transistor.
Claim 11
Dependent Claim
67 words
The memory circuit as recited in claim 9 further includes a read transistor, wherein said read transistor is coupled between a drain of said storage transistor and a read bit line, and wherein said read transistor is configured to cause a voltage discharge on said read bit line, wherein said read bit line conveys a voltage corresponding to said memory value in response to said voltage discharge.
Claim 12
Dependent Claim
37 words
The memory circuit as recited in claim 10 further includes a read word line connected to a gate of said read transistor, wherein said read word line is configured to turn on and off said read transistor.
Claim 13
Dependent Claim
25 words
The memory circuit as recited in claim 1 wherein said offset voltage element includes a transistor coupled between said buffer and said first reference voltage.
Claim 14
Dependent Claim
31 words
The memory circuit as recited in claim 12, wherein said transistor is a diode-connected transistor, wherein a gate of said diode-connected transistor is coupled to a drain of said diode-connected transistor.
Claim 15
Dependent Claim
21 words
The memory circuit as recited in claim 13, wherein said offset voltage equals a threshold voltage level of said diode-connected transistor.
Claim 16
Dependent Claim
72 words
The memory circuit as recited in claim 3 wherein said offset voltage element is formed by a pullup transistor coupled to said second reference voltage, wherein said pullup transistor is configured to be active during times at which said first transistor is on, and wherein said offset voltage is determined by the voltage established across said first transistor during times at which said first transistor and said pullup transistor are both on.
Claim 17
Dependent Claim
231 words
A memory circuit comprising: a memory array including at least one three-transistor memory cell wherein said three-transistor memory cell is configured to store a memory value on a capacitance formed by a storage transistor and a first reference voltage, and wherein said storage transistor is coupled between a write transistor and a read transistor, and wherein said write transistor is further coupled to a write bit line, and wherein said write transistor is configured to convey write data on said write bit line to be written to said storage transistor, and wherein said read transistor is further coupled to a read bit line, wherein said read transistor is configured to cause said memory value to be conveyed on said read bit line; and a write control unit coupled to said write bit line and said first reference voltage, wherein said write control unit includes: a buffer coupled to said write bit line, wherein said buffer is configured to convey a first output voltage on said write bit line in response to a first input voltage, and wherein said first output voltage establishes a first output logic state; and an offset voltage element coupled to said buffer, wherein said offset voltage element is configured to cause said first output voltage to be offset from said first reference voltage by an amount determined by an offset voltage established across said offset voltage element.
Claim 18
Dependent Claim
231 words
A memory circuit comprising: a memory array including at least one three-transistor memory cell wherein said three-transistor memory cell is configured to store a memory value on a capacitance formed by a storage transistor and a first reference voltage, and wherein said storage transistor is coupled between a write transistor and a read transistor, and wherein said write transistor is further coupled to a write bit line, and wherein said write transistor is configured to convey write data on said write bit line to be written to said storage transistor, and wherein said read transistor is further coupled to a read bit line, wherein said read transistor is configured to cause said memory value to be conveyed on said read bit line; and a write control unit coupled to said write bit line and said first reference voltage, wherein said write control unit includes: a buffer coupled to said write bit line, wherein said buffer is configured to convey a first output voltage on said write bit line in response to a first input voltage, and wherein said first output voltage establishes a first output logic state; and an offset voltage element coupled to said buffer, wherein said offset voltage element is configured to cause said first output voltage to be offset from said first reference voltage by an amount determined by an offset voltage established across said offset voltage element.
Claim 19
Dependent Claim
55 words
The memory circuit as recited in claim 16 wherein said buffer is coupled to a second reference voltage, and wherein said buffer is further configured to convey a second output voltage on said write bit line in response to a second input voltage, and wherein said second output voltage establishes a second output logic state.
Claim 20
Dependent Claim
52 words
The memory circuit as recited in claim 17 wherein said buffer includes a first transistor and a second transistor, wherein said first transistor is configured to turn on in response to said first input voltage, and wherein said second transistor is configured to turn on in response to said second input voltage.
Claim 21
Dependent Claim
43 words
The memory circuit as recited in claim 16 wherein said offset voltage element is formed by a diode-connected transistor coupled between said buffer and said reference voltage, wherein a gate of said diode-connected transistor is coupled to a drain of said diode-connected transistor.
Claim 22
Dependent Claim
21 words
The memory circuit as recited in claim 19 wherein said offset voltage equals a threshold voltage level of said diode-connected transistor.
References Cited (Backward Citations)
US5285414A
Cited
US5414656A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |