Semiconductor device capacitor having lower electrodes separated by low dielectric spacer material

Claim 2

A semiconductor device having a capacitor, said semiconductor device comprising: a plurality of lower electrodes each having side surfaces; a spacer formed on each of the side surfaces of said lower electrodes, said spacer comprising a material having a low dielectric constant, and at least two of said spacers and corresponding lower electrodes forming rounded edges, the height of said spacers not exceeding the height of said lower electrodes; a ferroelectric film formed over said plurality of lower electrodes and over said spacers, including over said rounded edges; and an upper electrode formed over said ferroelectric film including the film formed over said rounded edges.

Claim 3

A semiconductor device according to claim 1, wherein said spacer comprises a material selected from the group comprising PE--SiO 2 , CVD oxide, Si x N y , BN, BPSG, PSG, USG and BSG.

Claim 4

A semiconductor device according to claim 1, wherein at least one space is formed between said electrodes, and wherein said material having a low dielectric constant fills said at least one space.

Claim 5

A semiconductor device according to claim 2, wherein at least one space is formed between said lower electrodes, and wherein said material having a low dielectric constant fills said at least one space.

Claim 6

The semiconductor device according to claim 1, wherein said ferroelectric film is formed on said plurality of lower electrodes, and further wherein said ferroelectric film is formed on said spacer.

Claim 7

The semiconductor device according to claim 1, wherein said upper electrode is formed on said ferroelectric film.

Claim 8

The semiconductor device according to claim 5, wherein said upper electrode is formed on said ferroelectric film.

Claim 9

The semiconductor device according to claim 1, further comprising: a semiconductor substrate having an active region and a pair of transistors formed in said active region, said pair of transistors comprising a common drain region, gate regions and source regions; a bit line connected to said common drain region; and means for forming a conductive path between said lower electrodes and respective ones of said source regions; and a planarization layer formed over said semiconductor substrate; said plurality of lower electrodes being formed over said planarization layer.

Claim 10

A semiconductor device having a capacitor, said semiconductor device comprising: at least two lower electrodes arranged to form a space therebetween, said electrodes including respective inner side surfaces, forming respective opposing sides of said space, and respective outer side surfaces; a spacer material formed on each of said respective inner and outer side surfaces and at least partially filling said space, said spacer material having a low dielectric constant, and at least two of said spacers and corresponding lower electrodes forming rounded edges, the height of said spacers not exceeding the height of said lower electrodes; a ferroelectric film formed over said at least two lower electrodes and over said spacer material, including over said rounded edges; and at least one upper electrode formed over said ferroelectric film including the film formed over said rounded edges.

Claim 11

A semiconductor device having a capacitor, said semiconductor device comprising: at least two lower electrodes arranged to form a space therebetween, said electrodes including respective inner side surfaces, forming respective opposing sides of said space, and respective outer side surfaces; a spacer material formed on each of said respective inner and outer side surfaces and at least partially filling said space, said spacer material having a low dielectric constant, and at least two of said spacers and corresponding lower electrodes forming rounded edges, the height of said spacers not exceeding the height of said lower electrodes; a ferroelectric film formed over said at least two lower electrodes and over said spacer material, including over said rounded edges; and at least one upper electrode formed over said ferroelectric film including the film formed over said rounded edges.

Claim 12

The semiconductor device according to claim 9, wherein said spacer material comprises a material selected from the group comprising PE--SiO 2 , CVD oxide, Si x N y , BN, BPSG, PSG, USG and BSG.

Claim 13

The semiconductor device according to claim 9, wherein said semiconductor device comprises a dynamic random access memory device.

Claim 14

The semiconductor device according to claim 9, wherein said ferroelectric film has a dielectric constant of at least 1,000.

Claim 15

The semiconductor device according to claim 9, wherein said ferroelectric film comprises a material selected from the group comprising PZT, PbTiO 3 (PLT), PbLaZrTiO 3 (PLZT), SrTiO 3 (STO), BST, LiNbO 3 (LNO).

Claim 16

The semiconductor device according to claim 9, further comprising: a semiconductor substrate having an active region and a pair of transistors formed in said active region, said pair of transistors comprising a common drain region, gate regions and source regions; a bit line connected to said common drain region; and means for forming a conductive path between said lower electrodes and respective ones of said source regions; and a planarization layer formed over said semiconductor substrate; said plurality of lower electrodes being formed over said planarization layer.

Claim 17

The semiconductor device according to claim 1, wherein said rounded edges reduce the possibility that portions of said ferroelectric film over said rounded edges are weakened relative to other portions of said ferroelectric film.

Claim 18

The semiconductor device according to claim 9, wherein said rounded edges reduce the possibility that portions of said ferroelectric film over said rounded edges are weakened relative to other portions of said ferroelectric film.