Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction

Claim 1

A process for fabricating capacitors having a ferroelectric dielectric layer within a memory array that can be operated in both dynamic and non-volatile modes, said array having a conventional stacked-cell layout in which a series of substantially parallel, spaced apart wordlines, each of which is dielectrically coated on its lower, upper and lateral surfaces, traverses a substrate in which have been created a multiplicity of bipartite active areas which are insulated from one another by field oxide regions, each of the parts of each bipartite active area corresponding to the domain of an individual cell, and containing a storage-node contact region, the pair of domains constituting an active area being separated by a shared central region where bitline contact is made, the region of each domain between that domain's storage-node contact region and the shared bitline contact region being subjacent a wordline and forming the channel of that cell's access transistor, said array also having a series of substantially parallel, spaced-apart bitlines, each of which is dielectrically coated on its upper and lateral surfaces, and which overlie and intersect the dielectrically- coated wordlines, said process commencing at a stage in the manufacturing process where storage-node contact regions are exposed by masking the array with a storage-node contact photomask and performing an etch to clear the substrate in those regions, and said process comprising the following sequence of steps: a) conformal deposition of an in-situ doped storage-node polysilicon layer to a depth greater than that necessary to completely fill any inter-wordline and inter-bitline gaps; b) planarization of the storage-node poly layer to a level at which poly still covers the entire array; c) deposition of a conductive barrier layer on top of the planarized storage-node poly layer; d) deposition of a disposable polymer layer on top of the barrier layer; e) masking the disposable polymer layer with a photomask which patterns storage-node capacitor plates; f) anisotropically etching the disposable polymer layer, the barrier layer and the storage-node poly layer in a single step in order to create non-contiguous disposable layer, barrier layer, and storage-node poly layer remnants; g) blanket deposition of a cell-isolation dielectric layer at a temperature sufficiently low to prevent decomposition of the disposable polymer layer remnants, said cell-isolation layer being of sufficient depth to completely fill gaps between the disposable layer remnants; h) planarization of the cell-isolation dielectric layer to a level that exposes each disposable polymer layer remnant; i) removal of the disposable polymer layer remnants; j) deposition of a ferroelectric dielectric layer; k) annealing the ferroelectric dielectric layer; and l) deposition of a cell plate layer;