Fabricating method of dynamic random access memory

Claim 1

A fabricating method of a dynamic random access memory, comprising: providing a substrate including at least a metal oxide semiconductor which comprises a gate, a spacer around a side wall of the gate, a source/drain, and a field oxide layer; forming and patterning an insulation layer to form a first opening therein, and to expose a part of the source/drain; forming and patterning a first heavily doped polysilicon layer and a tungsten silicide layer to form a plurality of openings therein on the substrate; patterning the first heavily doped polysilicon layer and the tungsten layer to form a bit line which coupling with the source/drain by the first opening; forming a first oxide layer and a first dielectric layer on the insulation layer and the bit line; planarizing the first dielectric layer by a step of flow; forming and patterning a silicon nitride to form a plurality of second openings therein on the first dielectric layer, and to expose the first dielectric layer; forming and patterning a second oxide layer; removing the first dielectric layer, the first oxide layer, and the insulation layer within the second openings to form a plurality of vias, and to expose the source/drain; forming a second heavily doped polysilicon layer of hemispherical grains over the substrate; forming a second dielectric layer on the second heavily doped polysilicon layer of hemispherical grains; filling the vias with the second dielectric layers which is thicker than the second oxide layer; removing the second dielectric layer, the polysilicon layer of hemispherical grains and the second heavily doped polysilicon layer with the second oxide layer as a stop layer; and removing the second oxide layer and the second dielectric layer by wet etching with the silicon nitride layer as a stop layer.