System for a primary BIOS ROM recovery in a dual BIOS ROM computer system

Claim 2

A basic input-output memory recovery system for use on a computer, the system comprising: first and second basic input-output system (BIOS) memories, each having a plurality of locations containing data values representing a series of computer program instructions to initialize the computer and each having an enable input, a predetermined one of said locations in said first BIOS memory containing an error detection data value based on said data values in the remaining locations of said first BIOS memory; an error detection circuit to analyze the entire BIOS program contents of the locations in said first BIOS memory and said predetermined location in said first BIOS memory to detect errors in said first BIOS memory, said error detection circuit generating an error signal upon detection of errors in said first BIOS memory; and an enabling circuit to disable said first BIOS memory enable input and to enable said second BIOS memory enable input in response to said error signal.

Claim 3

The system of claim 1 wherein said error detection value in said predetermined location in said first BIOS memory contains a check sum data value indicative of said data values, and said error detection circuit uses said checksum data value to detect errors in said data values.

Claim 4

The system of claim 1 wherein said series of instructions in said first BIOS memory is identical to said series of instructions in said second BIOS memory.

Claim 5

The system of claim 1 wherein said first BIOS memory is a programmable memory, the system further including a programming circuit to reprogram said first BIOS programmable memory with said series of computer instructions from said second BIOS memory if said error detection circuit generates an error signal.

Claim 6

The system of claim 4 wherein said error detection circuit sets a data flag as said error signal, said programming circuit reprogramming said first BIOS programmable memory in response to said data flag.

Claim 7

The system of claim 4 wherein said first BIOS programmable memory is a flash programmable read-only memory.

Claim 8

The system of claim 1 wherein said series of computer instructions include instructions to load said data values into a random access memory in a power on self-test mode, the system further including a memory loader to load said data values into said random access memory, said memory loader loading said data values into said random access memory, said memory loader loading said data values into said random access memory from said first BIOS memory if said error signal was not generated, and loading said data values into said random access memory from said second BIOS memory if said error signal was generated.

Claim 9

The system of claim 7 wherein said first BIOS memory is a programmable memory, the system further including a programming circuit to reprogram said first BIOS programmable memory with said data loaded into said random access memory as part of said power on self-test.

Claim 10

The system of claim 1 wherein said error detection value in said predetermined location is said first BIOS memory contains a cyclic redundancy check (CRC) data value indicative of data values for said data, and said error detection circuit uses said CRC data value to detect errors in said data values.

Claim 11

The system of claim 1 wherein said second BIOS memory contains a plurality of locations containing data values and a predetermined one of said plurality of locations in said second BIOS memory contains an error detection data value based on said data values in the remaining ones of said plurality of locations in said second BIOS memory, said error detection circuit analyzing the BIOS program contents of said second BIOS memory and said error detection data value in said predetermined location in said second BIOS memory, when said second BIOS memory is enabled, to detect errors in said second BIOS memory, said error detection circuit generating a halt signal to halt operation of the computer upon detection of errors in said second BIOS memory.

Claim 12

A basic input-output memory recovery system for use on a computer, the system comprising: a first basic input-output system (BIOS) programmable memory having a plurality of locations containing data values representing a series of computer program instructions to initialize the computer, said first BIOS programmable memory having a programming input and an enable input, a predetermined one of said plurality of locations containing an error detection data value based on said data values in the remaining ones of said plurality of locations; an error detection circuit to analyze the entire BIOS program contents in said plurality of locations and said error detection data value to detect errors in any of said plurality of data values, said error detection circuit generating an error signal upon detection of errors in any of said plurality of data values; a second memory containing at least a portion of said series of computer instructions, said second BIOS memory having an enable input; an enabling circuit to disable said first BIOS programmable memory enable input and to enable said second BIOS memory chip enable input in response to said error signal; a random access memory to store computer instructions; a memory loader to copy said series of institutions from said second memory to said random access memory if said error detection circuit has generated said error signal; and a programming circuit to reprogram said first BIOS programmable memory with the contents of said random access memory if said error detection circuit has generated said error signal.

Claim 13

A basic input-output memory recovery system for use on a computer, the system comprising: a first basic input-output system (BIOS) programmable memory having a plurality of locations containing data values representing a series of computer program instructions to initialize the computer, said first BIOS programmable memory having a programming input and an enable input, a predetermined one of said plurality of locations containing an error detection data value based on said data values in the remaining ones of said plurality of locations; an error detection circuit to analyze the entire BIOS program contents in said plurality of locations and said error detection data value to detect errors in any of said plurality of data values, said error detection circuit generating an error signal upon detection of errors in any of said plurality of data values; a second memory containing at least a portion of said series of computer instructions, said second BIOS memory having an enable input; an enabling circuit to disable said first BIOS programmable memory enable input and to enable said second BIOS memory chip enable input in response to said error signal; a random access memory to store computer instructions; a memory loader to copy said series of institutions from said second memory to said random access memory if said error detection circuit has generated said error signal; and a programming circuit to reprogram said first BIOS programmable memory with the contents of said random access memory if said error detection circuit has generated said error signal.

Claim 14

The system of claim 11 wherein said first BIOS programmable memory is a flash programmable read-only memory.

Claim 15

The system of claim 11 wherein said second BIOS memory is a flash programmable read-only memory.

Claim 16

The system of claim 11 wherein said first BIOS programmable memory contains a check sum data value indicative of said data values for said plurality of locations in said first BIOS programmable memory, and said error detection circuit uses sand checksum data value to detect errors in any of said data values.

Claim 17

The system of claim 11 wherein said series of computer instructions include instructions to load said data into said random access memory in a power on self-test mode.

Claim 18

The system of claim 11 wherein said error detection circuit sets a data flag as said error signal, said programming circuit reprogramming said first BIOS programmable memory in response to said data flag.

Claim 19

The system of claim 11 wherein said error detection value in said predetermined location in said first BIOS programmable memory contains a cyclic redundancy check (CRC) data value indicative of said data values for said plurality of locations, and said error detection circuit uses said CRC data value to detect errors in any of said data values.

Claim 20

The system of claim 11 wherein said second BIOS memory contains a plurality of locations containing data values and a predetermined one of said plurality of locations in said second BIOS memory contains an error detection data value based on said data values in the remaining ones of said plurality of locations in said second BIOS memory, said error detection circuit analyzing the program contents of said second BIOS memory and said error detection data value in said predetermined location in said second BIOS memory, when said second BIOS memory is enabled, to detect errors in said second BIOS memory, said error detection circuit generating a halt signal to halt operation of the computer upon detection of errors in said second BIOS memory.