Patent US1707140A successfully refreshed from Google Patents.
Patent US5793694A successfully refreshed from Google Patents.
US5793694A
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Semiconductor integrated circuit device having means for peak current reduction
Assignee: Hitachi Ltd
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Filing: 1996-12-17
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Granted: 1998-08-11
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Expires: 2016-12-17
Abstract
Abstract The present invention is a method and apparatus for reducing the peak current for all the bit mats during a CAS-before-RAs refresh operation of a DRAM. To this end, a circuit is created to detect a CAS-before-RAS refresh operation. When a CBR refresh is detected, the amplifying of the bit mats are offset from each other, thereby staggering the time when each bit mat draws its peak current. In an alternative embodiment, when a CBR refresh is detected, the activation of the word lines are offset from each other, thereby staggering the time when each bit mat draws its peak current.
Inventors
- 👤 Takesada Akiba
- 👤 Hiroshi Otori
- 👤 Masayuki Nakamura
- 👤 Adin Hyslop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
249 words
A semiconductor memory comprising: first and second memory blocks each of which has a plurality of bit lines, a plurality of word lines, a plurality of dynamic memory cells and a plurality of sense amplifiers respectively coupled to said plurality of bit lines; a first drive circuit which supplies operating current to said plurality of sense amplifiers in said first memory block; a second drive circuit which supplies operating current to said plurality of sense amplifiers in said second memory block; a third drive circuit which selects one of said plurality of word lines in said first memory block; a fourth drive circuit which selects one of said plurality of word lines in said second memory block; a timing signal generator which outputs a first timing signal and a second timing signal that is delayed relative to said first timing signal; and a control circuit which selects one of said first and second memory blocks in a normal operation mode and selects both of said first and second memory blocks in a refresh operation mode, wherein, in said normal operation mode, a corresponding one of said first and second drive circuits and a corresponding one of said third and fourth drive circuits are activated in response to said first timing signal; and wherein, in said refresh operation mode, said first and third drive circuit are activated in response to said first timing signal and said second and fourth drive circuits are activated in response to said second timing signal.
Claim 2
Dependent Claim
249 words
A semiconductor memory comprising: first and second memory blocks each of which has a plurality of bit lines, a plurality of word lines, a plurality of dynamic memory cells and a plurality of sense amplifiers respectively coupled to said plurality of bit lines; a first drive circuit which supplies operating current to said plurality of sense amplifiers in said first memory block; a second drive circuit which supplies operating current to said plurality of sense amplifiers in said second memory block; a third drive circuit which selects one of said plurality of word lines in said first memory block; a fourth drive circuit which selects one of said plurality of word lines in said second memory block; a timing signal generator which outputs a first timing signal and a second timing signal that is delayed relative to said first timing signal; and a control circuit which selects one of said first and second memory blocks in a normal operation mode and selects both of said first and second memory blocks in a refresh operation mode, wherein, in said normal operation mode, a corresponding one of said first and second drive circuits and a corresponding one of said third and fourth drive circuits are activated in response to said first timing signal; and wherein, in said refresh operation mode, said first and third drive circuit are activated in response to said first timing signal and said second and fourth drive circuits are activated in response to said second timing signal.
Claim 3
Dependent Claim
24 words
A semiconductor memory according to claim 1, wherein said refresh operation mode is a CBR (column address strobe-before-row address strobe signal) refresh operation mode.
Claim 4
Dependent Claim
40 words
A semiconductor memory device according to claim 2, wherein said timing signal generator has a delay circuit, said second timing signal is output through said delay circuit, and said first timing signal is output without going through said delay circuit.
Claim 5
Dependent Claim
270 words
A semiconductor memory device comprising: a first memory cell array and a second memory cell array, each of which has a plurality of bit lines, a plurality of word lines and a plurality of dynamic memory cells; a timing signal generator which outputs a first timing signal and a second timing signal that is delayed relative to said first timing signal; a first driver which selects one of said plurality of word lines in said first memory cell array; a second driver which selects one of said plurality of word lines in said second memory cell array; a first sense amplifier group including a plurality of sense amplifiers that correspond to said plurality of bit lines in said first memory cell array; a second sense amplifier group including a plurality of sense amplifiers that correspond to said plurality of bit lines in said second memory cell array; and a selecting circuit that selects one or both of said first and second memory cell arrays, wherein, when one of said first and second memory cell arrays is selected, a corresponding one of said first and second drivers and said plurality of sense amplifiers in the corresponding one of selected sense amplifier groups operate in response to said first timing signal, and wherein, when both of said first and second memory cell arrays are selected, said first driver and said plurality of sense amplifiers in said first sense amplifier group operate in response to said first timing signal and said second driver and said plurality of sense amplifiers in said second sense amplifier group operate in response to said second timing signal.
Claim 6
Dependent Claim
270 words
A semiconductor memory device comprising: a first memory cell array and a second memory cell array, each of which has a plurality of bit lines, a plurality of word lines and a plurality of dynamic memory cells; a timing signal generator which outputs a first timing signal and a second timing signal that is delayed relative to said first timing signal; a first driver which selects one of said plurality of word lines in said first memory cell array; a second driver which selects one of said plurality of word lines in said second memory cell array; a first sense amplifier group including a plurality of sense amplifiers that correspond to said plurality of bit lines in said first memory cell array; a second sense amplifier group including a plurality of sense amplifiers that correspond to said plurality of bit lines in said second memory cell array; and a selecting circuit that selects one or both of said first and second memory cell arrays, wherein, when one of said first and second memory cell arrays is selected, a corresponding one of said first and second drivers and said plurality of sense amplifiers in the corresponding one of selected sense amplifier groups operate in response to said first timing signal, and wherein, when both of said first and second memory cell arrays are selected, said first driver and said plurality of sense amplifiers in said first sense amplifier group operate in response to said first timing signal and said second driver and said plurality of sense amplifiers in said second sense amplifier group operate in response to said second timing signal.
Claim 7
Dependent Claim
39 words
A semiconductor memory device according to claim 4, wherein said timing generator has a delay circuit, said second timing signal is output through said delay circuit, and said first timing signal is output without going through said delay circuit.
Claim 8
Dependent Claim
45 words
A semiconductor memory device according to claim 5, wherein said selecting circuit selects both of said first and second memory arrays in a refresh operating mode, and wherein said selecting circuit selects one of said first and second memory arrays in the normal operating mode.
Claim 9
Dependent Claim
35 words
A semiconductor memory device according to claim 6, further comprising a refresh mode detecting circuit, wherein said timing signal generator is controlled on the basis of a signal output from said refresh mode detecting circuit.
Claim 10
Dependent Claim
31 words
A semiconductor memory device according to claim 7, wherein said first and second timing signals are generated on the basis of an external timing signal supplied to said semiconductor memory device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |