Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation

Claim 2

An interleaved cache memory system for use in a computer having an address bus and a data bus for carrying burst accesses with an initial address and multiple data items and a processor clock, the cache memory system providing zero wait-state burst access to stored data following commencement of a read cycle, comprising: an array of asynchronous memory having address inputs and forming a cache address space, said array of memory partitioned into an even memory bank and an odd memory bank for storing data corresponding to even and odd addresses provided to the address inputs; burst logic for generating a first address signal for provision to a first address input of said even memory bank and a second address signal for provision to a second address input of said odd memory bank, said first and second address signals, in conjunction with additional address signals provided by an address bus, specifying a particular cache data item within said even memory bank and said odd memory bank, respectively; and control circuitry coupled to said burst logic, said address inputs of said even memory bank and said odd memory bank, and at least one signal on the address bus, wherein said control circuitry asynchronously passes the at least one signal from the address bus to at least one of said first and second address inputs of said even memory bank and said odd memory bank when the initial address is provided for the burst access, and wherein said control circuitry provides said first and second address signals to said first and second address inputs of said even and odd memory banks, respectively, synchronous with the processor clock for the remainder of the burst access.

Claim 3

The cache memory system of claim 1, further comprising additional arrays of memory partitioned into equal numbers of additional even memory banks and additional odd memory banks, wherein the address inputs to each of said even memory banks are essentially identical and wherein the address inputs to each of said odd memory banks are essentially identical.

Claim 4

The cache memory system of claim 2, further comprising: a tag memory coupled to the address bus for storing labels corresponding to the contents of each of said memory arrays; a tag address comparator, coupled to the address bus and said tag memory, for comparing stored labels to specified address bits of the address bus to determine which, if any, of said memory arrays contains data corresponding to a given address, said tag address comparator providing at least one memory array select signal based on the comparison; and output multiplexor circuitry having inputs individually coupled to the outputs of each of said even and odd memory banks, said output multiplexor circuitry providing one of the memory bank outputs to a processor data bus based upon said at least one memory array select signal and a memory bank select signal provided by said burst logic.

Claim 5

The cache memory system of claim 2, having a total of four even memory banks and a total of four odd memory banks.

Claim 6

The cache memory system of claim 1, wherein said burst logic generates said first address signal and said second address signal in accordance with a predetermined burst ordering scheme.

Claim 7

The cache memory system of claim 5, wherein said predetermined burst ordering scheme is a Pentium® burst sequence.

Claim 8

The cache memory system of claim 5, wherein said predetermined burst ordering scheme is a linear burst sequence.

Claim 9

A computer system, comprising: a processor; a processor bus coupled to said processor having address and data portions for carrying burst accesses with an initial address and multiple data items and a processor clock; a memory controller coupled to the processor bus and further coupled to a system bus; a main memory device coupled to said processor bus and said memory controller; a mass data storage device coupled to said system bus for providing data to said processor and said main memory device; and an interleaved cache memory system coupled to the processor bus for providing said processor with an intermediate source of frequently accessed data stored in said main memory, said cache memory system providing zero wait-state burst access to the duplicated data following commencement of a burst read cycle, said cache memory system comprising: an array of asynchronous memory having address inputs and forming a cache address space, said array of memory partitioned into an even memory bank and an odd memory bank for storing cache data corresponding to even and odd addresses provided to the address inputs; burst logic for generating a first address signal for provision to a first address input of said even memory bank and a second address signal for provision to a second address input of said odd memory bank, said first and second address signals, in conjunction with additional address signals provided by said processor address bus, specifying a particular cache data item within said even memory bank and said odd memory bank, respectively; and control circuitry coupled to said burst logic, said address inputs of said even memory bank and said odd memory bank, and at least one signal on said address bus, wherein said control circuitry asynchronously passes the at least one signal from the address bus to at least one of said first and second address inputs of said even memory bank and said odd memory bank when the initial address is provided for the burst access, and wherein said control circuitry provides said first and second address signals to said first and second address inputs of said even and odd memory banks, respectively, synchronous with the processor clock for the remainder of the burst access.

Claim 10

A computer system, comprising: a processor; a processor bus coupled to said processor having address and data portions for carrying burst accesses with an initial address and multiple data items and a processor clock; a memory controller coupled to the processor bus and further coupled to a system bus; a main memory device coupled to said processor bus and said memory controller; a mass data storage device coupled to said system bus for providing data to said processor and said main memory device; and an interleaved cache memory system coupled to the processor bus for providing said processor with an intermediate source of frequently accessed data stored in said main memory, said cache memory system providing zero wait-state burst access to the duplicated data following commencement of a burst read cycle, said cache memory system comprising: an array of asynchronous memory having address inputs and forming a cache address space, said array of memory partitioned into an even memory bank and an odd memory bank for storing cache data corresponding to even and odd addresses provided to the address inputs; burst logic for generating a first address signal for provision to a first address input of said even memory bank and a second address signal for provision to a second address input of said odd memory bank, said first and second address signals, in conjunction with additional address signals provided by said processor address bus, specifying a particular cache data item within said even memory bank and said odd memory bank, respectively; and control circuitry coupled to said burst logic, said address inputs of said even memory bank and said odd memory bank, and at least one signal on said address bus, wherein said control circuitry asynchronously passes the at least one signal from the address bus to at least one of said first and second address inputs of said even memory bank and said odd memory bank when the initial address is provided for the burst access, and wherein said control circuitry provides said first and second address signals to said first and second address inputs of said even and odd memory banks, respectively, synchronous with the processor clock for the remainder of the burst access.

Claim 11

The computer system of claim 8, wherein said cache memory system further comprises additional arrays of memory partitioned into equal numbers of additional even memory banks and additional odd memory banks, and wherein the address inputs to each of said even memory banks are essentially identical and the address inputs to each of said odd memory banks are essentially identical.

Claim 12

The computer system of claim 9, wherein the cache memory system further comprises: a tag memory coupled to the processor address bus for storing labels corresponding to the contents of each of said memory arrays; a tag address comparator, coupled to the processor address bus and said tag memory, for comparing stored labels to specified address bits of the processor address bus to determine which, if any, of said memory arrays contains data corresponding to a given address, said tag address comparator providing at least one memory array select signal based on the comparison; and output multiplexor circuitry having inputs individually coupled to the outputs of each of said even and odd memory banks, said output multiplexor circuitry providing one of the memory bank outputs to the processor data bus based upon said at least one memory array select signal and a memory bank select signal provided by said burst logic.

Claim 13

Cache control logic for use in an interleaved cache memory system, the cache control logic enabling zero wait-state burst access to stored data following commencement of a burst read cycle, comprising: burst logic for generating a first address signal for provision to a first address input of an even memory bank and a second address signal for provision to a second address input of an odd memory bank; and control circuitry coupled to said burst logic and capable of coupling to at least one signal of an address bus, wherein said control circuitry asynchronously passes the at least one signal from the address bus to at least one of the first and second address inputs of an even memory bank or an odd memory bank when the initial address is provided for the burst access, and wherein said control circuitry provides said first and second address signals to the first and second address inputs of the even and odd memory banks, respectively, synchronous with a processor clock for the remainder of the burst access.

Claim 14

Cache control logic for use in an interleaved cache memory system, the cache control logic enabling zero wait-state burst access to stored data following commencement of a burst read cycle, comprising: burst logic for generating a first address signal for provision to a first address input of an even memory bank and a second address signal for provision to a second address input of an odd memory bank; and control circuitry coupled to said burst logic and capable of coupling to at least one signal of an address bus, wherein said control circuitry asynchronously passes the at least one signal from the address bus to at least one of the first and second address inputs of an even memory bank or an odd memory bank when the initial address is provided for the burst access, and wherein said control circuitry provides said first and second address signals to the first and second address inputs of the even and odd memory banks, respectively, synchronous with a processor clock for the remainder of the burst access.

Claim 15

The cache control logic of claim 11, further comprising: a tag memory capable of coupling to an address bus for storing labels corresponding to the contents of memory arrays; a tag address comparator, coupled to said tag memory and capable of coupling to an address bus, for comparing stored labels to specified address bits of an address bus to determine which, if any, of a plurality of memory arrays contains data corresponding to a given address, said tag address comparator providing at least one memory array select signal based on the comparison.

Claim 18

The method of claim 13, wherein the predetermined burst ordering scheme is a Pentium® burst sequence.

Claim 19

The method of claim 13, wherein the predetermined burst ordering scheme is a linear burst sequence.