Patent US5793677A successfully refreshed from Google Patents.
US5793677A
Expired / Lapsed
US
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Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
Assignee: Cypress Semiconductor Corp
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Filing: 1996-06-18
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Granted: 1998-08-11
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Expires: 2016-06-18
Abstract
Abstract The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.
Inventors
- 👤 Chung-You Hu
- 👤 Yu Sun
- 👤 Chi Chang
- 👤 Sameer Haddad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:49
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
120 words
A method for inhibiting random programming in a Flash memory, comprising: a) providing a first voltage in a channel region of a floating gate device in which programming is undesirable, the first voltage being initially high enough to prevent the floating gate device from being programmed; b) providing a second voltage in a first select device included in a select means coupled to the floating gate device in which programming is undesirable, wherein the second voltage is less than the first voltage; and c) providing a third voltage in a second select device, the second select device being included within the select means and coupled to the first select device, wherein the third voltage is less than the second voltage.
Claim 2
Independent Claim
120 words
A method for inhibiting random programming in a Flash memory, comprising: a) providing a first voltage in a channel region of a floating gate device in which programming is undesirable, the first voltage being initially high enough to prevent the floating gate device from being programmed; b) providing a second voltage in a first select device included in a select means coupled to the floating gate device in which programming is undesirable, wherein the second voltage is less than the first voltage; and c) providing a third voltage in a second select device, the second select device being included within the select means and coupled to the first select device, wherein the third voltage is less than the second voltage.
Claim 3
Dependent Claim
11 words
The method of claim 1, wherein the third voltage is zero.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein the first and second select devices are floating gate devices.
Claim 5
Dependent Claim
14 words
The method of claim 1, wherein the first and second select devices are transistors.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein the first and second select devices include at least one transistor and at least one floating gate device.
Claim 7
Independent Claim
123 words
A system for inhibiting random programming in a Flash memory, comprising: means for providing a first voltage in a channel region of a floating gate device in which programming is undesirable, the first voltage being initially high enough to prevent the floating gate device from being programmed; means for providing a second voltage in a first select device included in a select means coupled to the floating gate device in which programming is undesirable, wherein the second voltage is less than the first voltage; and means for providing a third voltage in a second select device, the second select device being included within the select means and coupled to the first select device, wherein the third voltage is less than the second voltage.
Claim 8
Independent Claim
123 words
A system for inhibiting random programming in a Flash memory, comprising: means for providing a first voltage in a channel region of a floating gate device in which programming is undesirable, the first voltage being initially high enough to prevent the floating gate device from being programmed; means for providing a second voltage in a first select device included in a select means coupled to the floating gate device in which programming is undesirable, wherein the second voltage is less than the first voltage; and means for providing a third voltage in a second select device, the second select device being included within the select means and coupled to the first select device, wherein the third voltage is less than the second voltage.
Claim 9
Dependent Claim
11 words
The system of claim 6, wherein the third voltage is zero.
Claim 10
Dependent Claim
16 words
The system of claim 6, wherein the first and second select devices are floating gate devices.
Claim 11
Dependent Claim
14 words
The system of claim 6, wherein the first and second select devices are transistors.
Claim 12
Dependent Claim
24 words
The system of claim 6, wherein the first and second select devices include at least one transistor and at least one floating gate device.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |