Double polysilicon EEPROM cell and corresponding manufacturing process and programming method

Claim 2

An EEPROM memory cell, comprising: a selection transistor having a selection gate that sets the selection transistor in a conductive state upon application of a voltage; a storage transistor having a floating gate and a control gate that are capacitively coupled by an intermediate dielectric layer; an oxide layer positioned beneath both the selection gate of the selection transistor and the floating gate of the storage transistor; and a graded junction located immediately beneath the oxide layer, the graded junction having a first region that laterally extends beneath both the selection gate of the selection transistor and the floating gate of the storage transistor, the graded junction having a second region that is formed in the first region, is shallower than the first region, and laterally extends beneath both the selection gate and the floating gate, the first region laterally extending beneath the selection gate and the floating gate farther than the second region.

Claim 3

The EEPROM cell according to claim 1 wherein the oxide layer portion positioned below the selection gate of the selection transistor is a gate oxide and the oxide layer portion positioned below the floating gate of the storage transistor is a thin tunnel oxide.

Claim 4

The EEPROM memory cell of claim 1 wherein the first and second regions of the graded junction are formed using respective first and second concentrations of a same dopant type and wherein the first concentration is a lighter concentration than the second concentration.

Claim 5

The EEPROM memory cell of claim 3 wherein the type of dopant is a donor type dopant and wherein the first concentration is a concentration of phosphorous atoms and wherein the second concentration is a concentration of arsenic atoms.

Claim 6

A memory cell, comprising: a first semiconductor region having a first doping profile and formed in a substrate having a surface; a second semiconductor region formed in said substrate and having a second doping profile different from said first doping profile; a third semiconductor region having said first doping profile and formed in said substrate; a selection channel formed in said substrate and interposed between and contiguous with said first semiconductor region, and said second semiconductor region said selection channel being associated with no memory cells other than said memory cell; a storage channel formed in said substrate and interposed between and contiguous with said second semiconductor region and said third semiconductor region; a gate insulator formed on said selection and storage channels; a selection gate formed on said gate insulator in alignment with said selection channel; a floating gate formed on said gate insulator in alignment with said storage channel; an interpoly dielectric formed on said floating gate; and a control gate formed on said interpoly dielectric.

Claim 7

A memory cell, comprising: a first semiconductor region having a first doping profile and formed in a substrate having a surface; a second semiconductor region formed in said substrate and having a second doping profile different from said first doping profile; a third semiconductor region having said first doping profile and formed in said substrate; a selection channel formed in said substrate and interposed between and contiguous with said first semiconductor region, and said second semiconductor region said selection channel being associated with no memory cells other than said memory cell; a storage channel formed in said substrate and interposed between and contiguous with said second semiconductor region and said third semiconductor region; a gate insulator formed on said selection and storage channels; a selection gate formed on said gate insulator in alignment with said selection channel; a floating gate formed on said gate insulator in alignment with said storage channel; an interpoly dielectric formed on said floating gate; and a control gate formed on said interpoly dielectric.

Claim 8

The memory cell of claim 5 wherein said second semiconductor region is doped N type.

Claim 9

The memory cell of claim 5 wherein said gate insulator comprises an oxide.

Claim 10

The memory cell of claim 5 wherein a portion of said gate insulator that is in alignment with said floating gate forms a tunnel oxide.

Claim 11

The memory cell of claim 5 wherein: said first semiconductor region forms a drain of the memory cell; and said third semiconductor region forms a source of the memory cell.

Claim 12

The memory cell of claim 9 wherein said drain is a lightly doped drain and said source is a lightly doped source.

Claim 13

The memory cell of claim 5 wherein said second semiconductor region includes a first portion having a first concentration of a first dopant of a predetermined type and a second portion having a second concentration of a second dopant of said predetermined type.

Claim 14

The memory cell of claim 11 wherein said first concentration is substantially less than said second concentration.

Claim 15

The memory cell of claim 11 wherein: said first dopant includes phosphorous; and said second dopant includes arsenic.

Claim 16

The memory cell of claim 11 wherein said first portion extends a first lateral distance beneath said selection gate and a second lateral distance beneath said floating gate.

Claim 17

The memory cell of claim 11 wherein: said first portion extends a first lateral distance beneath said selection gate and a second lateral distance beneath said floating gate; said second portion extends a third lateral distance beneath said selection gate and a fourth lateral distance beneath said floating gate; and said first and second lateral distances respectively exceed said third and fourth lateral distances.

Claim 18

A memory circuit, having a semiconductor substrate that has a substrate surface, the memory circuit comprising: one or more word lines; one or more bit lines; one or more control lines; and an array of memory cells each including, a drain formed in said substrate and coupled to one of said bit lines, a source formed in said substrate, a selection channel formed in said substrate and contiguous with said drain, a storage channel formed in said substrate and contiguous with said source, a gate insulator disposed on said substrate surface and in alignment with said selection and storage channels, a selection gate disposed on said gate insulator in alignment with said selection channel and coupled to one of said word lines, a floating gate disposed on said gate insulator in alignment with said storage channel, an interpoly dielectric disposed on said floating gate, a control gate disposed on said interpoly dielectric in alignment with said floating gate and coupled to one of said control lines, and a graded junction formed in said substrate and interposed between and contiguous with said storage and selection channels, said graded junction including a first section doped with a first concentration of a first dopant of a predetermined type and a second section doped with a second concentration of a second dopant of said predetermined type, said second section laterally extending beneath said storage gate and said floating gate, said first section extending deeper into said substrate than said second section and laterally extending farther beneath said storage gate and floating gate than said second section.

Claim 19

A memory circuit, having a semiconductor substrate that has a substrate surface, the memory circuit comprising: one or more word lines; one or more bit lines; one or more control lines; and an array of memory cells each including, a drain formed in said substrate and coupled to one of said bit lines, a source formed in said substrate, a selection channel formed in said substrate and contiguous with said drain, a storage channel formed in said substrate and contiguous with said source, a gate insulator disposed on said substrate surface and in alignment with said selection and storage channels, a selection gate disposed on said gate insulator in alignment with said selection channel and coupled to one of said word lines, a floating gate disposed on said gate insulator in alignment with said storage channel, an interpoly dielectric disposed on said floating gate, a control gate disposed on said interpoly dielectric in alignment with said floating gate and coupled to one of said control lines, and a graded junction formed in said substrate and interposed between and contiguous with said storage and selection channels, said graded junction including a first section doped with a first concentration of a first dopant of a predetermined type and a second section doped with a second concentration of a second dopant of said predetermined type, said second section laterally extending beneath said storage gate and said floating gate, said first section extending deeper into said substrate than said second section and laterally extending farther beneath said storage gate and floating gate than said second section.

Claim 20

The memory circuit of claim 16 wherein said predetermined dopant type is donor type.

Claim 21

The memory circuit of claim 16 wherein said second concentration is substantially greater than said first concentration.

Claim 22

The memory circuit of claim 16 wherein: said first dopant includes phosphorous; and said second dopant includes arsenic.

Claim 23

The memory circuit of claim 16 wherein said selection, floating, and control gates comprise polysilicon.

Claim 24

The memory curcuit of claim 16 wherein said gate insulator includes a first portion that is in alignment with said floating gate and includes a second portion that is in alignment with said selection gate, said first portion significantly thinner than said second portion.

Claim 25

The memory circuit of claim 16 wherein said drain has a first region having a first concentration of said predetermined type of dopant, and has a second region having a second concentration of said predetermined type of dopant, said second region positioned between and contiguous with said first region and said selection channel; said source has a third region having a third concentration of said predetermined type of dopant, and has a fourth region having a fourth concentration of said predetermined type of dopant, said fourth region positioned between and contiguous with said third region and said selection channel, said third region laterally spaced from said floating gate; and said first and third concentrations respectively exceed said second and fourth concentrations.