US5790843A
Expired / Lapsed
US
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System for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodes
Assignee: International Business Machines Corp
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Filing: 1996-09-19
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Granted: 1998-08-04
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Expires: 2016-09-19
Abstract
Abstract Described herein is a system and method for providing instruction dependent execution control on a microprocessor device. The system and method utilize instruction match register/execution control register (IMR/ECR) pairs to first identify known problematic instructions and to then alter control of the microprocessor in a preselected manner when processing each problematic instruction. The invention contemplates the use of numerous control options for altering control of the microprocessor.
Inventors
- 👤 John Michael Borkenhagen
- 👤 William Thomas Flynn
- 👤 Philip Rodgers Hillier, III
- 👤 Andrew Henry Wottreng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F8/00; G06F8/60; G06F8/65; G06F8/66; G06F9/32; G06F9/322; G06F9/328
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
144 words
A microprocessor device comprising: an instruction match register, said instruction match register having a first memory location for storing a predetermined binary opcode; an instruction matching system, said instruction matching system having a compare apparatus for comparing said predetermined binary opcode with each of a plurality of program instructions; an execution control register, said execution control system having a second memory location for storing one of a plurality of control codes; and an execution control system, said execution control system including logic for detecting a match from said instruction matching system, decoding logic for decoding said control code, and control logic for forcing one of a plurality of alternate microprocessor operations, wherein at least one the plurality of alternate microprocessor operations causes the microprocessor device to execute each of the plurality of program instructions with a predetermined alteration to the timing of the execution.
Claim 2
Dependent Claim
144 words
A microprocessor device comprising: an instruction match register, said instruction match register having a first memory location for storing a predetermined binary opcode; an instruction matching system, said instruction matching system having a compare apparatus for comparing said predetermined binary opcode with each of a plurality of program instructions; an execution control register, said execution control system having a second memory location for storing one of a plurality of control codes; and an execution control system, said execution control system including logic for detecting a match from said instruction matching system, decoding logic for decoding said control code, and control logic for forcing one of a plurality of alternate microprocessor operations, wherein at least one the plurality of alternate microprocessor operations causes the microprocessor device to execute each of the plurality of program instructions with a predetermined alteration to the timing of the execution.
Claim 3
Dependent Claim
18 words
The microprocessor device of claim 1 wherein said plurality of alternate microprocessor operations includes an instruction dispatch process.
Claim 4
Dependent Claim
16 words
The microprocessor device of claim 2 wherein said instruction dispatch process dispatches a specified instruction normally.
Claim 5
Dependent Claim
21 words
The microprocessor device of claim 2 wherein said instruction dispatch process dispatches a specified instruction alone in a single clock cycle.
Claim 6
Dependent Claim
24 words
The microprocessor device of claim 2 wherein said instruction dispatch process dispatches a specified instruction alone in a single clock cycle with a delay.
Claim 7
Dependent Claim
23 words
The microprocessor device of claim 1 further comprising a pipeline, and wherein said plurality of alternate microprocessor operations include an instruction execution process.
Claim 8
Dependent Claim
19 words
The microprocessor device of claim 6 wherein said instruction execution process aborts a subsequent instruction and restarts said pipeline.
Claim 9
Dependent Claim
24 words
The microprocessor device of claim 6 wherein said instruction execution process aborts a subsequent instruction, performs a context synchronize operation and restarts said pipeline.
Claim 10
Dependent Claim
24 words
The microprocessor device of claim 6 wherein said instruction execution process aborts a subsequent instruction, performs a super synchronized operation and restarts said pipeline.
Claim 11
Dependent Claim
27 words
The microprocessor device of claim 6 wherein said instruction execution process aborts a current and any subsequent instructions in said pipeline and restarts with said current instruction.
Claim 12
Dependent Claim
22 words
The microprocessor device of claim 6 wherein said instruction execution process aborts a current instruction and interrupts to a predetermined interrupt vector.
Claim 13
Dependent Claim
22 words
The microprocessor device of claim 1 wherein said of plurality of alternate microprocessor operations include means for forcing an instruction cache miss.
Claim 14
Dependent Claim
25 words
The microprocessor device of claim 1 wherein said plurality of alternate microprocessor operations include means for delaying a restart by a predetermined number of cycles.
Claim 15
Dependent Claim
72 words
A microprocessor device comprising: instruction matching means for comparing preselected binary opcodes with a plurality of program instructions prior to an execution of each of said program instructions; execution means for executing program instructions; and execution control means for causing one of a plurality of preselected modified microprocessor operations upon the occurrence of a match by said instruction matching means, wherein the preselected modified microprocessor operation operates independently of the execution means.
Claim 16
Dependent Claim
72 words
A microprocessor device comprising: instruction matching means for comparing preselected binary opcodes with a plurality of program instructions prior to an execution of each of said program instructions; execution means for executing program instructions; and execution control means for causing one of a plurality of preselected modified microprocessor operations upon the occurrence of a match by said instruction matching means, wherein the preselected modified microprocessor operation operates independently of the execution means.
Claim 17
Dependent Claim
23 words
The microprocessor device of claim 14 wherein said execution control means is dependent upon a predetermined value stored in an execution control register.
Claim 18
Dependent Claim
20 words
The microprocessor device of claim 14 wherein said execution control means includes means for controlling the dispatching of program instructions.
Claim 19
Dependent Claim
20 words
The microprocessor device of claim 14 wherein said execution control means includes means for controlling the execution of program instructions.
Claim 20
Dependent Claim
24 words
The microprocessor device of claim 14 wherein said execution control means includes means to force an instruction cache miss on a fetch for restart/interrupt.
Claim 21
Dependent Claim
26 words
The microprocessor device of claim 14 wherein said execution control means includes means to force a delay in a restart by a predetermined number of cycles.
Claim 22
Dependent Claim
15 words
The microprocessor device of claim 14 wherein said instruction matching means includes an imask register.
Claim 23
Independent Claim
159 words
A method for realizing instruction-dependent execution control on a microprocessor that includes an instruction match register and an accompanying execution control register, said method comprising the steps of: loading an instruction opcode into said instruction match register; choosing one of a plurality of control options for handling program instructions that match said instruction opcode loaded into said instruction match register; loading a control code into said execution control register wherein said control codes includes encoded information to effectuate said chosen control option; commencing execution of a stream of program instructions; prior to the execution of each program instruction in said stream of program instructions, comparing each instruction with said instruction opcode loaded into said instruction match register; and upon a match between one of said program instructions and said instruction opcode, decoding said control code loaded into said execution control register and then altering microprocessor control such that the matched program instruction is executed with a predetermined timing alteration.
Claim 24
Independent Claim
159 words
A method for realizing instruction-dependent execution control on a microprocessor that includes an instruction match register and an accompanying execution control register, said method comprising the steps of: loading an instruction opcode into said instruction match register; choosing one of a plurality of control options for handling program instructions that match said instruction opcode loaded into said instruction match register; loading a control code into said execution control register wherein said control codes includes encoded information to effectuate said chosen control option; commencing execution of a stream of program instructions; prior to the execution of each program instruction in said stream of program instructions, comparing each instruction with said instruction opcode loaded into said instruction match register; and upon a match between one of said program instructions and said instruction opcode, decoding said control code loaded into said execution control register and then altering microprocessor control such that the matched program instruction is executed with a predetermined timing alteration.
Claim 25
Dependent Claim
26 words
The method of claim 21 wherein said microprocessor includes a plurality of instruction match registers wherein each instruction match register has an associated execution control register.
Claim 26
Dependent Claim
21 words
The method of claim 21 wherein said step of altering microprocessor control includes the step of causing a nonuniform dispatch operation.
Claim 27
Dependent Claim
21 words
The method of claim 21 wherein said step of altering microprocessor control includes the step of causing a nonuniform execution operation.
Claim 28
Dependent Claim
26 words
The method of claim 21 wherein said step of altering microprocessor control includes the step of causing an instruction cache miss on a fetch for restart.
Claim 29
Dependent Claim
25 words
The method of claim 21 wherein said step of altering microprocessor control includes the step of delaying a restart by a predetermined number of cycles.
Claim 30
Dependent Claim
143 words
A microprocessor device comprising: a plurality of instruction match registers for storing a plurality of instruction opcodes; an instruction matching system, said instruction matching system for comparing each of said plurality of program instructions with each of said plurality of instruction opcodes; a plurality of execution control registers for storing a plurality of control codes wherein each of said plurality of execution control registers is logically coupled to one of said plurality of instruction match registers; and an execution control system, said execution control system including: decoding logic for decoding one of said control codes when a program instruction match occurs in an associated instruction match register; control logic for altering control of said microprocessor device when processing said matched program instruction; and detecting logic for determining whether a match occurred in two or more instruction match registers within a predetermined time frame.
Claim 31
Dependent Claim
143 words
A microprocessor device comprising: a plurality of instruction match registers for storing a plurality of instruction opcodes; an instruction matching system, said instruction matching system for comparing each of said plurality of program instructions with each of said plurality of instruction opcodes; a plurality of execution control registers for storing a plurality of control codes wherein each of said plurality of execution control registers is logically coupled to one of said plurality of instruction match registers; and an execution control system, said execution control system including: decoding logic for decoding one of said control codes when a program instruction match occurs in an associated instruction match register; control logic for altering control of said microprocessor device when processing said matched program instruction; and detecting logic for determining whether a match occurred in two or more instruction match registers within a predetermined time frame.
Claim 32
Dependent Claim
16 words
The microprocessor device of claim 27 wherein each instruction match register includes an associated IMASK register.
Claim 33
Dependent Claim
16 words
The microprocessor device of claim 27 wherein said control logic includes logic for altering instruction dispatch.
Claim 34
Dependent Claim
16 words
The microprocessor device of claim 27 wherein said control logic includes logic for altering processor execution.
Claim 35
Dependent Claim
24 words
The microprocessor device of claim 27 wherein said control logic includes logic for forcing an instruction cache miss on a fetch for a restart.
Claim 36
Dependent Claim
22 words
The microprocessor device of claim 27 wherein said control logic includes logic for delaying a restart by a predetermined number of cycles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |