Patent US5790832A successfully refreshed from Google Patents.
US5790832A
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Method and apparatus for tracing any node of an emulation
Assignee: Mentor Graphics Corp
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Filing: 1996-04-23
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Granted: 1998-08-04
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Expires: 2016-04-23
Abstract
Abstract A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence identifies how values of the hidden nodes are to be determined based on corresponding ones of the physically observable nodes. The value of a hidden node is determined by obtaining the values of the corresponding physically observable nodes and identifying the value of the hidden node based on the correspondence between the corresponding physically observable nodes and the hidden node.
Inventors
- 👤 Jean Barbier
- 👤 Olivier LePape
- 👤 Frederic Reblewski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:26
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
111 words
In an emulation system, a method for tracing hidden nodes of a circuit design, the method comprising the steps of: (a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes; (b) accessing values of the plurality of physically observable nodes; and (c) determining the values of the hidden nodes based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the hidden nodes.
Claim 2
Dependent Claim
111 words
In an emulation system, a method for tracing hidden nodes of a circuit design, the method comprising the steps of: (a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes; (b) accessing values of the plurality of physically observable nodes; and (c) determining the values of the hidden nodes based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the hidden nodes.
Claim 3
Dependent Claim
51 words
The method of claim 1, wherein the maintaining step (a) comprises the steps of: generating a first list listing the physically observable nodes; and generating a second list listing the hidden nodes, wherein each node of the second list is defined in terms of selected ones of the physically observable nodes.
Claim 4
Dependent Claim
61 words
The method of claim 2, wherein the maintaining step (a) further comprises the steps of: generating a truth table vector for each node of the second list; and storing the truth table vectors with the second list, wherein each truth table vector identifies the values of the corresponding hidden node as a function of the values of the physically observable nodes.
Claim 5
Dependent Claim
20 words
The method of claim 1, further comprising the step of: outputting the values of the hidden nodes to a user.
Claim 6
Independent Claim
126 words
A method for tracing any node of a circuit design in an emulator, the method comprising the steps of: (a) generating a physically observable net list identifying a first plurality of nodes of the circuit design which can be physically observed in the emulator; (b) creating a hidden net list identifying a second plurality of nodes of the circuit design, wherein each node of the second plurality of nodes is hidden in a logic element of the emulator; (c) determining a first set of input nodes from the first plurality of nodes; and (d) using the first set of input nodes to identify a value of a signal at a first hidden node, wherein the first hidden node is one of the second plurality of nodes.
Claim 7
Independent Claim
126 words
A method for tracing any node of a circuit design in an emulator, the method comprising the steps of: (a) generating a physically observable net list identifying a first plurality of nodes of the circuit design which can be physically observed in the emulator; (b) creating a hidden net list identifying a second plurality of nodes of the circuit design, wherein each node of the second plurality of nodes is hidden in a logic element of the emulator; (c) determining a first set of input nodes from the first plurality of nodes; and (d) using the first set of input nodes to identify a value of a signal at a first hidden node, wherein the first hidden node is one of the second plurality of nodes.
Claim 8
Dependent Claim
39 words
The method of claim 5, further comprising the step of generating a first truth table vector which encodes a set of possible values for the first hidden node based on different values of the first set of input nodes.
Claim 9
Dependent Claim
28 words
The method of claim 6, further comprising the step of using the values of the first set of input nodes as an index into the truth table vector.
Claim 10
Dependent Claim
69 words
The method of claim 5, wherein the using step (d) comprises the steps of: accessing the set of input nodes to identify a value of a signal at a second hidden node, wherein the second hidden node is one of the second plurality of nodes; and using the value of the signal at the second hidden node to determine the value of the signal at the first hidden node.
Claim 11
Dependent Claim
102 words
A program storage device readable by an emulation system, the device embodying a program of instructions executable by the emulation system to perform method steps for tracing a node of a circuit design, wherein the node is hidden in a logic element of the emulation system, said method steps comprising: (a) identifying a set of physically observable input signals corresponding to the node; (b) indexing into a truth table vector using values of the set of physically observable input signals; and (c) determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.
Claim 12
Dependent Claim
102 words
A program storage device readable by an emulation system, the device embodying a program of instructions executable by the emulation system to perform method steps for tracing a node of a circuit design, wherein the node is hidden in a logic element of the emulation system, said method steps comprising: (a) identifying a set of physically observable input signals corresponding to the node; (b) indexing into a truth table vector using values of the set of physically observable input signals; and (c) determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.
Claim 13
Dependent Claim
32 words
The program storage device of claim 9, further comprising the step of storing a set of node identifications corresponding to the set of physically observable input signals in an observable net file.
Claim 14
Dependent Claim
23 words
The program storage device of claim 9, further comprising the step of generating a hidden net list which stores the truth table vector.
Claim 15
Dependent Claim
28 words
The program storage device of claim 11, wherein the hidden net list also stores the node and a set identifier of the set of physically observable input signals.
Claim 16
Dependent Claim
150 words
A program storage device readable by a computer system, the device embodying a program of instructions executable by the computer system to perform method steps for tracing hidden nodes of a circuit design, said method steps comprising: (a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes; (b) accessing values of the plurality of physically observable nodes from an emulator coupled to the computer system upon receiving a request for the value of a first hidden node; and (c) determining the value of the first hidden node based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the first hidden node.
Claim 17
Dependent Claim
150 words
A program storage device readable by a computer system, the device embodying a program of instructions executable by the computer system to perform method steps for tracing hidden nodes of a circuit design, said method steps comprising: (a) maintaining a correspondence between a plurality of physically observable nodes of the circuit design and the hidden nodes, including how values of the hidden nodes are to be determined based on the plurality of physically observable nodes; (b) accessing values of the plurality of physically observable nodes from an emulator coupled to the computer system upon receiving a request for the value of a first hidden node; and (c) determining the value of the first hidden node based at least in part on both the values of one or more of the plurality of physically observable nodes and the correspondence between the plurality of physically observable nodes and the first hidden node.
Claim 18
Dependent Claim
53 words
The program storage device of claim 13, wherein the maintaining step (a) comprises the steps of: generating a first list listing the physically observable nodes; and generating a second list listing the hidden nodes, wherein each node of the second list is defined in terms of selected ones of the physically observable nodes.
Claim 19
Dependent Claim
52 words
The program storage device of claim 13, wherein the determining step (c) comprises the steps of: accessing values of the plurality of physically observable nodes to identify a value of a second hidden node; and using the value of the second hidden node to determine the value of the first hidden node.
Claim 20
Dependent Claim
30 words
The program storage device of claim 13, wherein the program of instructions are further to perform the method step of: outputting the values of the hidden nodes to a user.
Claim 21
Dependent Claim
79 words
An emulation system which traces a node of a circuit design, the emulation system comprising: a logic element in which the node is hidden; means for identifying a set of physically observable input signals corresponding to the node; means for indexing into a truth table vector using values of the set of physically observable input signals; and means for determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.
Claim 22
Dependent Claim
79 words
An emulation system which traces a node of a circuit design, the emulation system comprising: a logic element in which the node is hidden; means for identifying a set of physically observable input signals corresponding to the node; means for indexing into a truth table vector using values of the set of physically observable input signals; and means for determining the value of the hidden node by accessing the value of the truth table vector indicated by the indexing.
Claim 23
Dependent Claim
26 words
The emulation system of claim 17, further comprising the means for storing a set of node identifications corresponding to the set of physically observable input signals.
Claim 24
Dependent Claim
21 words
The emulation system of claim 17, further comprising means for generating a hidden net list which stores the truth table vector.
Claim 25
Dependent Claim
27 words
The emulation system of claim 19, wherein the hidden net list also stores the node and a set identifier of the set of physically observable input signals.
References Cited (Backward Citations)
US5448496A
Cited
US5084824A
Cited
US5416719A
Cited
US5638493A
Cited
US5659484A
Cited
US5598510A
Cited
US5586046A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |