Operand prefetch table

Claim 2

In a data processing system wherein sequences of instructions stored in a main memory are executed by at least one processor, a method of transferring from said main memory to a high speed buffer operand data utilized by said processor when executing one or more of said sequences of instructions, the method comprising the steps of: storing operand miss addresses in entries of a table, wherein each entry of said table includes an operand miss address that identifies an operand miss and an instruction address field that identifies an instruction that caused said operand miss identified by said operand miss address of said entry, fetching at least one instruction from said main memory to said high speed buffer according to a fetch control signal; and prefetching operand data identified by an operand miss address stored in at least one entry of said table from said main memory to said high speed buffer when said fetch control signal corresponds to an instruction address field of said at least one entry.

Claim 3

The method of claim 1, wherein each entry of said table includes a confirmation bit corresponding to said operand miss address of said entry, and wherein first operand data identified by an operand miss address stored in a first entry of said table is prefetched from said main memory to said high speed buffer when i) said fetch control signal corresponds to said instruction address field of said first entry, and ii) said confirmation bit of said first entry is set to a first predetermined value thereby indicating that said first operand data should be prefetched from said main memory to said high speed buffer.

Claim 4

The method of claim 2, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, further comprising the steps of: identifying a cache miss address; identifying a particular entry whose instruction address field corresponds to said cache miss address; and if said confirmation bit of said particular entry is set to said first predetermined value and sum of said operand miss address and said stride field of said particular entry does not equal said cache miss address, setting said confirmation bit to a second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer, updating said stride field of said particular entry to difference between said operand miss address of said entry and said cache miss address, and updating said operand miss address of said particular entry to said cache miss address.

Claim 5

The method of claim 2, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, further comprising the steps of: identifying a cache miss address; identifying a particular entry whose instruction address field corresponds to said cache miss address; and if said confirmation bit of said particular entry is set to said first predetermined value and sum of said operand miss address and said stride field of said particular entry equals said cache miss address, updating said operand miss address of said particular entry to said cache miss address.

Claim 6

The method of claim 2, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, further comprising the steps of: identifying a cache miss address; identifying a particular entry whose instruction address field corresponds to said cache miss address; and if said confirmation bit of said particular entry is set to a second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer and sum of said operand miss address and said stride field of said particular entry does not equal said cache miss address, updating said stride field of said particular entry to difference between said operand miss address of said entry and said cache miss address, and updating said operand miss address of said particular entry to said cache miss address.

Claim 7

The method of claim 2, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, further comprising the step of: identifying a cache miss address; identifying a particular entry whose instruction address field corresponds to said cache miss address; and if said confirmation bit of said particular entry is set to a second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer and sum of said operand miss address and said stride field of said particular entry equals said cache miss address, setting said confirmation bit of said particular entry to said first predetermined value.

Claim 8

The method of claim 2, further comprising the step of updating said confirmation bit of a particular entry upon determining that a prefetch request corresponding to said entry was made but not utilized by said processor.

Claim 9

The method of claim 1, wherein said fetch control signal is an address within said main memory of an instruction fetch block that comprises said at least one instruction.

Claim 10

The method of claim 1, wherein said high speed buffer includes a data cache integral with an instruction cache.

Claim 11

The method of claim 1, wherein said high speed buffer includes a data cache separate from an instruction cache.

Claim 12

The method of claim 1, wherein said high speed buffer includes a prefetch buffer separate from said data cache.

Claim 13

A data processing system comprising: a main memory that stores sequences of instructions to be executed by at least one processor; a high speed buffer that stores operand data utilized by said processor when executing one or more of said sequences of instructions; instruction fetch logic that fetches at least one instruction from said main memory to said high speed buffer according to a fetch control signal; a table for storing entries each including an operand miss address that identifies an operand miss and an instruction address field that identifies an instruction that caused said operand miss identified by said operand miss address of said entry; and operand prefetch control means for prefetching operand data identified by an operand miss address stored in at least one entry of said table from said main memory to said high speed buffer when said fetch control signal corresponds to an instruction address field of said at least one entry.

Claim 14

A data processing system comprising: a main memory that stores sequences of instructions to be executed by at least one processor; a high speed buffer that stores operand data utilized by said processor when executing one or more of said sequences of instructions; instruction fetch logic that fetches at least one instruction from said main memory to said high speed buffer according to a fetch control signal; a table for storing entries each including an operand miss address that identifies an operand miss and an instruction address field that identifies an instruction that caused said operand miss identified by said operand miss address of said entry; and operand prefetch control means for prefetching operand data identified by an operand miss address stored in at least one entry of said table from said main memory to said high speed buffer when said fetch control signal corresponds to an instruction address field of said at least one entry.

Claim 15

The system of claim 12, wherein each entry of said table includes a confirmation bit corresponding to said operand miss address of said entry, and wherein said operand prefetch control means prefetches first operand data identified by an operand address stored in a first entry of said table from said main memory to said high speed buffer when i) said fetch control signal corresponds to said instruction address field of said first entry, and ii) said confirmation bit of said first entry is set to a first predetermined value thereby indicating that said first operand data should be prefetched from said main memory to said high speed buffer.

Claim 16

The system of claim 12, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, said system further comprising means for identifying a cache miss address; and wherein said operand prefetch control means identifies a particular entry whose instruction address field corresponds to said cache miss address, and if said confirmation bit of said particular entry is set to said first predetermined value and sum of said operand miss address and said stride field of said particular entry does not equal said cache miss address, sets said confirmation bit of said particular entry to a second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer, updates said stride field of said particular entry to difference between said operand miss address of said entry and said cache miss address, and updates said operand miss address of said particular entry to said cache miss address.

Claim 17

The system of claim 12, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, said system further comprising means for identifying a cache miss address; and wherein said operand prefetch control means identifies a particular entry whose instruction address field corresponds to said cache miss address, and if said confirmation bit of said particular entry is set to said first predetermined value and sum of said operand miss address and said stride field of said particular entry equals said cache miss address, updates said operand miss address of said particular entry to said cache miss address.

Claim 18

The system of claim 12, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, said system further comprising means for identifying a cache miss address; and wherein said operand prefetch control means identifies a particular entry whose instruction address field corresponds to said cache miss address, and if said confirmation bit of said particular entry is set to second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer and sum of said operand miss address and said stride field of said particular entry does not equal said cache miss address, updates said stride field of said particular entry to difference between said operand miss address of said entry and said cache miss address, and updates said operand miss address of said particular entry to said cache miss address.

Claim 19

The system of claim 12, wherein each entry further comprises a stride field that identifies offset from a subsequent operand miss to a next operand miss for said instruction identified by said instruction address field of said entry, said system further comprising means for identifying a cache miss address; and wherein said operand prefetch control means identifies a particular entry whose instruction address field corresponds to said cache miss address, and if said confirmation bit of said particular entry is set to a second predetermined value thereby indicating that operand data corresponding to said operand miss address of said particular entry should not be prefetched from said main memory to said high speed buffer and sum of said operand miss address and said stride field of said particular entry equals said cache miss address, sets said confirmation bit of said particular entry to said first predetermined value.

Claim 20

The system of claim 12, wherein said operand prefetch control means updates said confirmation bit of a particular entry upon determining that a prefetch request corresponding to said entry was made but not utilized by said processor.

Claim 21

The system of claim 12, wherein said fetch control signal is an address within said main memory of an instruction fetch block that comprises said at least one instruction.

Claim 22

The system of claim 12, wherein said high speed buffer includes a data cache integral with an instruction cache.

Claim 23

The system of claim 12, wherein said high speed buffer includes a data cache separate from an instruction cache.

Claim 24

The system of claim 12, wherein said high speed buffer includes a prefetch buffer separate from said data cache.