Patent US5789808A successfully refreshed from Google Patents.
US5789808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device structured to be less susceptible to power supply noise
Assignee: Mitsubishi Electric Corp
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Filing: 1996-12-03
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Granted: 1998-08-04
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Expires: 2016-12-03
Abstract
Abstract A lead frame of a DRAM chip includes a base end portion to which an external power supply potential ext•VCC is applied, and two branch portions branching away from the base end portion. A tip portion of one of these two branch portions is connected to an output buffer, and a tip portion of the other is connected to another circuit. Power supply noise generated at the output buffer passes through one of the branch portions to the outside, and will never reach another circuit through the other branch portion. Accordingly, a DRAM which is less susceptible to power supply noise can be provided.
Inventors
- 👤 Kyoji Yamasaki
- 👤 Mikio Asakura
- 👤 Tadaaki Yamauchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:28
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10W; H10W72/00; H10W44/00; H10W44/20; H10W44/203; H10W44/206; H10W70/00; H10W70/60; H10W72/50; H10W72/541; H10W72/5445; H10W72/5449; H10W72/547; H10W72/5473; H10W72/59; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
186 words
A semiconductor device having an internal circuit responsive to an external signal for carrying out a predetermined operation, comprising: first to third power supply pads each receiving an external power supply voltage; a boosting circuit receiving said external power supply voltage from said first power supply pad for boosting the external power supply voltage to produce a first internal power supply voltage for said internal circuit; a down-converting circuit receiving said external power supply voltage from said second power supply pad for down-converting the external power supply voltage to produce a second internal power supply voltage for said internal circuit; and an input circuit receiving said external power supply voltage from said third power supply pad for transmitting said external signal to said internal circuit, wherein a line for said external power supply voltage between said first power supply pad and said boosting circuit, a line for said external power supply voltage between said second power supply pad and said down-converting circuit, and a line for said external power supply voltage between said third power supply pad and said input circuit are insulated from each other.
Claim 2
Dependent Claim
186 words
A semiconductor device having an internal circuit responsive to an external signal for carrying out a predetermined operation, comprising: first to third power supply pads each receiving an external power supply voltage; a boosting circuit receiving said external power supply voltage from said first power supply pad for boosting the external power supply voltage to produce a first internal power supply voltage for said internal circuit; a down-converting circuit receiving said external power supply voltage from said second power supply pad for down-converting the external power supply voltage to produce a second internal power supply voltage for said internal circuit; and an input circuit receiving said external power supply voltage from said third power supply pad for transmitting said external signal to said internal circuit, wherein a line for said external power supply voltage between said first power supply pad and said boosting circuit, a line for said external power supply voltage between said second power supply pad and said down-converting circuit, and a line for said external power supply voltage between said third power supply pad and said input circuit are insulated from each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |