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US5789780A
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Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate
Assignee: Advanced Micro Devices Inc
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Filing: 1996-12-03
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Granted: 1998-08-04
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Expires: 2016-12-03
Abstract
Abstract An integrated circuit including a detached drain transistor comprising a semiconductor substrate, a gate dielectric, and a first and a second source/drain impurity distribution. The substrate includes a channel region laterally displaced between a first and a second source/drain region. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and includes a first and a second sidewall. The first and second sidewalls of the conductive gate are laterally displaced from channel boundaries of the first and second source/drain regions by a source/drain displacement. The first and second source/drain impurity distributions are substantially contained within the first and second source/drain regions respectively of the semiconductor substrate. Preferably, the transistor further includes a gate insulator formed in contact with the first and second sidewalls of the semiconductor substrate. Respective exterior sidewalls of the gate insulator are laterally displaced from the first and second sidewalls by a first displacement. The gate dielectric typically comprises an oxide having a thickness of approximately 20 to 200 angstroms while the conductive gate may comprise polysilicon having a sheet resistivity of less than approximately 500 Ω/square. A lateral dimension of the conductive gate is preferably less than 0.3 microns and the breakdown voltage of the transistor is greater than approximately 7 volts.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:01
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0221
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
138 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of-said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is less than approximately 0.3 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 2
Dependent Claim
138 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of-said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is less than approximately 0.3 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 3
Dependent Claim
143 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is in the range of approximately 0.2 to 0.3 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 4
Dependent Claim
143 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is in the range of approximately 0.2 to 0.3 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 5
Dependent Claim
143 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is in the range of approximately 0.1 to 0.2 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 6
Dependent Claim
143 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein a lateral dimension of said conductive gate is in the range of approximately 0.1 to 0.2 microns; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 7
Dependent Claim
138 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate; and wherein a breakdown voltage of said transistor is greater than approximately 7 volts.
Claim 8
Dependent Claim
138 words
A transistor comprising: a semiconductor substrate, wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate; and wherein a breakdown voltage of said transistor is greater than approximately 7 volts.
Claim 9
Dependent Claim
135 words
A transistor comprising: a semiconductor substrate wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein said source/drain displacement is approximately 200 to 300 angstroms; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
Claim 10
Dependent Claim
135 words
A transistor comprising: a semiconductor substrate wherein said semiconductor substrate comprises a channel region laterally displaced between a pair of detached source/drain regions; a gate dielectric formed on an upper surface of said semiconductor substrate; a conductive gate formed on said gate dielectric, wherein said conductive gate includes a first sidewall and a second sidewall, wherein said first and second sidewalls of said conductive gate are laterally displaced from respective channel boundaries of said pair of detached source/drain regions by a source/drain displacement such that a lateral dimension of said conductive gate is less than a lateral dimension between said pair of detached source/drain regions, and wherein said source/drain displacement is approximately 200 to 300 angstroms; and a source/drain impurity distribution substantially contained within said pair of detached source/drain regions respectively of said semiconductor substrate.
References Cited (Backward Citations)
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