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US5784016A
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Self-calibration technique for pipe line A/D converters
Assignee: Texas Instruments Inc
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Filing: 1996-11-01
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Granted: 1998-07-21
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Expires: 2016-11-01
Abstract
Abstract A new self calibration technique for pipe line A/D converters is presented. It consists of calibration by correcting the reference voltage to each stage by means of a tunable MOSFET attenuator. This simplifies the calibration circuit in each stage and shifts most of the calibration task to a hardware that is shared by all the stages.
Inventors
- 👤 K. Nagaraj
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:39
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1057; H03M1/1061; H03M1/12; H03M1/34; H03M1/38; H03M1/44; H03M1/442
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
122 words
A method of calibrating a pipe line A/D converter which comprises the steps of: correcting a reference voltage to each stage of the pipe line A/D converter by means of a tunable MOSFET attenuator; deriving tuning voltages for the different stages of the pipe line A/D converter in a master tuning circuit, wherein a single master tuning circuit sequentially serves all stages of the pipe line A/D converter, and wherein said single master tuning circuit consists of a capacitive multiplying DAC that is driven by a digital calibration word for the particular stage being refreshed; comparing the output of the multiplying DAC with the calibrated reference from the stage; and adjusting the tuning voltage to the particular stage until they are equal.
Claim 2
Independent Claim
122 words
A method of calibrating a pipe line A/D converter which comprises the steps of: correcting a reference voltage to each stage of the pipe line A/D converter by means of a tunable MOSFET attenuator; deriving tuning voltages for the different stages of the pipe line A/D converter in a master tuning circuit, wherein a single master tuning circuit sequentially serves all stages of the pipe line A/D converter, and wherein said single master tuning circuit consists of a capacitive multiplying DAC that is driven by a digital calibration word for the particular stage being refreshed; comparing the output of the multiplying DAC with the calibrated reference from the stage; and adjusting the tuning voltage to the particular stage until they are equal.
Claim 3
Dependent Claim
40 words
The method of claim 1 wherein said adjusting step comprises: generating a tuning voltage in said master tuning circuit; applying said tuning voltage to a pair of MOS transistors to generate said adjusted reference voltage from a fixed reference voltage.
Claim 4
Independent Claim
124 words
A method of calibrating a pipe line A/D converter which comprises the steps of: correcting a reference voltage to a plurality of stages of the pipe line A/D converter by means of a tunable MOSFET attenuator; deriving tuning voltages for the different stages of the pipe line A/D converter in a master tuning circuit, wherein a single master tuning circuit sequentially serves all stages of the pipe line AID converter, and wherein said single master tuning circuit consists of a capacitive multiplying DAC that is driven by a digital calibration word for the particular stage being refreshed; comparing the output of the multiplying DAC with the calibrated reference from the stage; and adjusting the tuning voltage to the particular stage until they are equal.
Claim 5
Independent Claim
124 words
A method of calibrating a pipe line A/D converter which comprises the steps of: correcting a reference voltage to a plurality of stages of the pipe line A/D converter by means of a tunable MOSFET attenuator; deriving tuning voltages for the different stages of the pipe line A/D converter in a master tuning circuit, wherein a single master tuning circuit sequentially serves all stages of the pipe line AID converter, and wherein said single master tuning circuit consists of a capacitive multiplying DAC that is driven by a digital calibration word for the particular stage being refreshed; comparing the output of the multiplying DAC with the calibrated reference from the stage; and adjusting the tuning voltage to the particular stage until they are equal.
Claim 6
Dependent Claim
40 words
The method of claim 3 wherein said adjusting step comprises: generating a tuning voltage in said master tuning circuit; applying said tuning voltage to a pair of MOS transistors to generate said adjusted reference voltage from a fixed reference voltage.
Claim 7
Dependent Claim
102 words
A pipe line A/D converter comprising: a predetermined number of pipe line A/D converter stages; a single master tuning circuit coupled to a plurality of said pipe line AID converter stages, said single master tuning circuit deriving tuning voltages for said plurality of pipe line A/D converter stages and consisting of a capacitive multiplying DAC that is driven by a digital calibration word for each particular stage of said plurality being refreshed; a comparator comparing an output of said multiplying DAC with a calibrated reference from the stage; and a tunable MOSFET attenuator for generating a calibrated reference voltage for each stage.
Claim 8
Dependent Claim
102 words
A pipe line A/D converter comprising: a predetermined number of pipe line A/D converter stages; a single master tuning circuit coupled to a plurality of said pipe line AID converter stages, said single master tuning circuit deriving tuning voltages for said plurality of pipe line A/D converter stages and consisting of a capacitive multiplying DAC that is driven by a digital calibration word for each particular stage of said plurality being refreshed; a comparator comparing an output of said multiplying DAC with a calibrated reference from the stage; and a tunable MOSFET attenuator for generating a calibrated reference voltage for each stage.
Claim 9
Dependent Claim
22 words
The apparatus of claim 5 wherein said single master tuning circuit is coupled to all stages of said pipe line A/D converter.
Claim 10
Dependent Claim
35 words
The apparatus of claim 5 wherein said MOSFET attenuator comprises a pair of MOSFET transistors each being coupled to a separate fixed reference voltage and to said tuning voltage for generating said calibrated reference voltage.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-07-20 | 2002-01-19 | 2002-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-20 | 2006-01-19 | 2006-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-20 | 2010-01-19 | 2010-07-21 | $7700.00 | Window Closed / Lapsed |