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US5780879A
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Field-effect transistor and method of manufacturing the same
Assignee: NEC Compound Semiconductor Devices Ltd
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Filing: 1997-05-30
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Granted: 1998-07-14
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Expires: 2017-05-30
Abstract
Abstract An FET includes a semi-insulating GaAs substrate, a buffer layer, a first graded layer, a channel layer, a second graded layer, a cap layer, source and drain electrodes, and a gate electrode. The buffer layer consists of a high-resistance semiconductor crystal exhibiting lattice matching with GaAs and is formed on the substrate. The first graded layer consists of an (AlzGa1-z)1-xInxP semiconductor crystal and is formed on the buffer layer such that the In content is gradually increased with distance from the buffer layer. The channel layer consists of an InyGa1-yAs semiconductor crystal and is formed on the graded layer. The second graded layer consists of an (AlzGa1-z)1-xInxP semiconductor crystal and is formed on the channel layer such that the In content is gradually decreased with distance from the channel layer. The cap layer consists of GaAs and is formed on the second graded layer. The source and drain electrodes are formed on the cap layer. The gate electrode is formed between the source and drain electrodes by removing the cap layer. An Al content z of each graded layer is 0 to 0.5. An In content y of the channel layer is 0.2 to 0.6. A method of manufacturing this FET is also disclosed.
Inventors
- 👤 Kosei Unozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
204 words
A field-effect transistor comprising a semi-insulating GaAs substrate, a buffer layer essentially consisting of a high-resistance semiconductor crystal exhibiting lattice matching with GaAs and formed on said semi-insulating GaAs substrate, a first graded layer essentially consisting of an (Al z Ga 1-z ) 1-x In x P semiconductor crystal and formed on said buffer layer such that an In content is gradually increased with distance from said buffer layer, a channel layer essentially consisting of an In y Ga 1-y As semiconductor crystal and formed on said first graded layer, a second graded layer essentially consisting of an (Al z Ga 1-z ) 1-x In x P semiconductor crystal and formed on said channel layer such that an In content is gradually decreased with distance from said channel layer, a cap layer consisting of GaAs and formed on said second graded layer, source and drain electrodes formed on said cap layer, and a gate electrode formed between said source and drain electrodes by removing said cap layer, wherein an Al content z of said first and second graded layers falls within a range of 0 to 0.5, and an In content y of said channel layer falls within a range of 0.2 to 0.6.
Claim 2
Dependent Claim
204 words
A field-effect transistor comprising a semi-insulating GaAs substrate, a buffer layer essentially consisting of a high-resistance semiconductor crystal exhibiting lattice matching with GaAs and formed on said semi-insulating GaAs substrate, a first graded layer essentially consisting of an (Al z Ga 1-z ) 1-x In x P semiconductor crystal and formed on said buffer layer such that an In content is gradually increased with distance from said buffer layer, a channel layer essentially consisting of an In y Ga 1-y As semiconductor crystal and formed on said first graded layer, a second graded layer essentially consisting of an (Al z Ga 1-z ) 1-x In x P semiconductor crystal and formed on said channel layer such that an In content is gradually decreased with distance from said channel layer, a cap layer consisting of GaAs and formed on said second graded layer, source and drain electrodes formed on said cap layer, and a gate electrode formed between said source and drain electrodes by removing said cap layer, wherein an Al content z of said first and second graded layers falls within a range of 0 to 0.5, and an In content y of said channel layer falls within a range of 0.2 to 0.6.
Claim 3
Dependent Claim
54 words
A transistor according to claim 1, wherein the In contents of said first and second graded layers at interfaces with said channel layer are controlled such that band gaps of both said first and second graded layers at the interfaces with said channel layer are higher than a band gap of said channel layer.
Claim 4
Dependent Claim
28 words
A transistor according to claim 1, wherein at least one of said first and second graded layers has an n-type doped electron donor layer on a channel side.
Claim 5
Dependent Claim
33 words
A transistor according to claim 1, wherein said second graded layer has an n-type doped electron donor layer on a channel layer side, and said channel layer is an n-type doped channel layer.
Claim 6
Dependent Claim
33 words
A transistor according to claim 2, wherein said second graded layer has an n-type doped electron donor layer on the channel layer side, and said channel layer is an n-type doped channel layer.
Claim 7
Dependent Claim
30 words
A transistor according to claim 1, wherein each of said first and second graded layers contains Al within a range in which the Al content z does not exceed 0.5.
Claim 8
Dependent Claim
20 words
A field-effect transistor wherein an In content y of said channel layer falls within a range of 0.5 to 0.6.
Claim 9
Dependent Claim
20 words
A field-effect transistor wherein an In content y of said channel layer falls within a range of 0.5 to 0.6.
Claim 10
Dependent Claim
28 words
A transistor according to claim 2, wherein at least one of said first and second graded layers has an n-type doped electron donor layer on a channel side.
References Cited (Backward Citations)
JPH04326734A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2005-07-13 | 2006-01-12 | 2006-07-14 | $3760.00 | Window Closed / Lapsed |
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