Patent US5778311A successfully refreshed from Google Patents.
US5778311A
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Intermittent operation receiver with variable pre-heat time for its phase-locked circuit
Assignee: Panasonic Holdings Corp
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Filing: 1996-06-28
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Granted: 1998-07-07
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Expires: 2016-06-28
Abstract
Abstract An intermittent operation receiver comprises a receiving circuit 8 receiving one of plural intermittent receiving operation information and data transmitted from a base station and generating its demodulated signal 24, a PLL circuit 7 including a voltage-controlled oscillator 5 and generating two kinds of local signals 25 and 26 different 90° in their phases which are sent to the receiving circuit 8 to process the input signal, and a data processing section 14 which receives the demodulated signal 24 from the receiving circuit 8, decodes the data to generate a first intermittent cycle generation timing signal 18 including a period corresponding to the cycle information of the intermittent receiving operation, and sends this first intermittent cycle generation timing signal 18 to receiving circuit 8 to control the power supply from its power source unit. Meanwhile, data processing section 14 selectively determines a pre-heat time t1, t2 or t3 in accordance with the designated intermittent operating cycle, generates a second intermittent cycle generation timing signal 19 involving the timing of the pre-heat time, and sends this second intermittent cycle generation timing signal 19 to the PLL circuit 7 to control the power supply from its power source unit.
Inventors
- 👤 Hideo Nakanishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:44
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0274; H04W52/028; H04W52/0283; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0802; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
214 words
An intermittent operation receiver comprising: a receiving circuit for receiving a control signal including at least one of plural intermittent operating cycles and data transmitted from a base station, and for generating a demodulated signal; a PLL circuit including a voltage-controlled oscillator for generating two kinds of local signals having a 90° phase difference which are sent to said receiving circuit to control processing of received signals; and a data processing section for receiving said demodulated signal from said receiving circuit, decoding said data and processing said control signal to generate a first intermittent cycle generation timing signal including a period corresponding to a designated intermittent operating cycle of said control signal, and sending out said first intermittent cycle generation timing signal to said receiving circuit to control a power supply for said receiving circuit, said data processing section selectively determining a pre-heat time in accordance with an intermittent operating cycle derived from said control signal, and generating a second intermittent cycle generation timing signal for timing said pre-heat time and generating said second intermittent cycle generation timing signal to said PLL circuit to control a power supply for said PLL circuit, thereby changing said pre-heat time of said PLL circuit in accordance with any modified intermittent operating cycle sent from said base station.
Claim 2
Dependent Claim
214 words
An intermittent operation receiver comprising: a receiving circuit for receiving a control signal including at least one of plural intermittent operating cycles and data transmitted from a base station, and for generating a demodulated signal; a PLL circuit including a voltage-controlled oscillator for generating two kinds of local signals having a 90° phase difference which are sent to said receiving circuit to control processing of received signals; and a data processing section for receiving said demodulated signal from said receiving circuit, decoding said data and processing said control signal to generate a first intermittent cycle generation timing signal including a period corresponding to a designated intermittent operating cycle of said control signal, and sending out said first intermittent cycle generation timing signal to said receiving circuit to control a power supply for said receiving circuit, said data processing section selectively determining a pre-heat time in accordance with an intermittent operating cycle derived from said control signal, and generating a second intermittent cycle generation timing signal for timing said pre-heat time and generating said second intermittent cycle generation timing signal to said PLL circuit to control a power supply for said PLL circuit, thereby changing said pre-heat time of said PLL circuit in accordance with any modified intermittent operating cycle sent from said base station.
Claim 3
Dependent Claim
72 words
The intermittent operation receiver in accordance with claim 1, further comprising a ROM for storing timing information for plural pre-heat times corresponding to said plural intermittent operating cycles, wherein said data processing section reads out timing information from said ROM relating to a pre-heat time for a designated intermittent operating cycle when intermittent operation cycle information is received from said base station, thereby determining timing for said intermittent cycle generation timing signal.
Claim 4
Dependent Claim
45 words
The intermittent operation receiver in accordance with claim 1, wherein said data processing section comprises a means for setting an initial intermittent operating cycle, so that said first and second intermittent cycle generation timing signals are determined in accordance with said initial intermittent operating cycle.
Claim 5
Dependent Claim
101 words
The intermittent operation receiver in accordance with claim 1, wherein said receiving circuit comprises: a first regulator circuit for receiving said first intermittent cycle generation timing signal from said data processing section and supplying a first power voltage to said receiving circuit in response to a timing of said first intermittent cycle generation timing signal, and a second regulator circuit for receiving said second intermittent cycle generation timing signal from said data processing section and supplying said PLL circuit with a second power voltage involving said pre-heat time in response to a timing of said second intermittent cycle generation timing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |