US5778210A
Expired / Lapsed
US
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Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
Assignee: Intel Corp
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Filing: 1996-01-11
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Granted: 1998-07-07
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Expires: 2016-01-11
Abstract
Abstract A method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time allows components within the processor to begin the steps of dispatch and execution of operations based on the speculated return of data for the operations at a predetermined time. After these steps have begun for an operation, a signal is received by one or more of these components if the operation cannot be completed at the speculated time. If the operation cannot be completed at the speculated time then the operation is canceled, recovering the state of the operation prior to the beginning of the steps of dispatch and execution.
Inventors
- 👤 Alexander P. Henstrom
- 👤 Robert W. Martell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3824; G06F9/3826; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
108 words
In a processor, a method for recovering an operation which has speculatively begun a series of stages for dispatching and executing the operation and which cannot be completed at a speculated time, the method comprising the steps of: (a) receiving a signal indicating that the operation cannot be completed at the speculated time; (b) canceling execution of the operation in response to the receiving of the signal, if the operation has been dispatched: (c) generating a bypass miss signal in response to the receiving of the signal; and (d) preventing the operation from dispatching, in response to the bypass miss signal, if the operation has not been dispatched.
Claim 2
Dependent Claim
108 words
In a processor, a method for recovering an operation which has speculatively begun a series of stages for dispatching and executing the operation and which cannot be completed at a speculated time, the method comprising the steps of: (a) receiving a signal indicating that the operation cannot be completed at the speculated time; (b) canceling execution of the operation in response to the receiving of the signal, if the operation has been dispatched: (c) generating a bypass miss signal in response to the receiving of the signal; and (d) preventing the operation from dispatching, in response to the bypass miss signal, if the operation has not been dispatched.
Claim 3
Dependent Claim
24 words
The method of claim 1, further comprising the step of preventing an entry of a reservation station, corresponding to the operation, from being deallocated.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein the bypass miss signal corresponds to a port of a reservation station from which the operation was or was to be dispatched.
Claim 5
Dependent Claim
39 words
The method of claim 1, further comprising the step of preventing a second operation from being dispatched from a reservation station, the second operation being ready for dispatch due to a speculated return of data at the speculated time.
Claim 6
Dependent Claim
152 words
In a microprocessor, a method of providing operations for execution by one or more execution units, the method comprising the steps of: (a) dispatching a first operation, wherein the first operation is unable to return its corresponding data prior to a predetermined time; (b) determining a second operation is ready to be dispatched prior to the predetermined time, the determining being based on a speculated return of the data corresponding to the first operation; (c) canceling execution of the second operation if the second operation has been dispatched, wherein the canceling is responsive to the first operation being unable to return the data prior to the predetermined time; (d) generating a bypass miss signal responsive to the first operation being unable to return the data prior to the predetermined time; and (e) preventing the second operation from dispatching, responsive to the bypass miss signal, if the second operation has not been dispatched.
Claim 7
Dependent Claim
152 words
In a microprocessor, a method of providing operations for execution by one or more execution units, the method comprising the steps of: (a) dispatching a first operation, wherein the first operation is unable to return its corresponding data prior to a predetermined time; (b) determining a second operation is ready to be dispatched prior to the predetermined time, the determining being based on a speculated return of the data corresponding to the first operation; (c) canceling execution of the second operation if the second operation has been dispatched, wherein the canceling is responsive to the first operation being unable to return the data prior to the predetermined time; (d) generating a bypass miss signal responsive to the first operation being unable to return the data prior to the predetermined time; and (e) preventing the second operation from dispatching, responsive to the bypass miss signal, if the second operation has not been dispatched.
Claim 8
Dependent Claim
25 words
The method of claim 5, further comprising the step of preventing an entry of a reservation station, corresponding to the second operation, from being deallocated.
Claim 9
Dependent Claim
29 words
The method of claim 5, wherein the bypass miss signal corresponds to a port of a reservation station from which the second operation was or was to be dispatched.
Claim 10
Dependent Claim
28 words
The method of claim 5, further comprising the step of clearing a physical destination address match bit corresponding to the second operation responsive to the bypass miss signal.
Claim 11
Dependent Claim
21 words
The method of claim 5, further comprising the step of generating a cancel schedule signal responsive to the bypass miss signal.
Claim 12
Dependent Claim
23 words
The method of claim 9, further comprising the step of preventing a third operation from being scheduled responsive to the cancel schedule signal.
Claim 13
Dependent Claim
43 words
The method of claim 5, further comprising the step of preventing a third operation from being dispatched from a reservation station, the third operation being ready for dispatch due to the speculated return of data at the predetermined time from the first operation.
Claim 14
Dependent Claim
25 words
The method of claim 5, further comprising the step of returning the second operation to its state prior to being determined ready to be dispatched.
Claim 15
Independent Claim
128 words
An apparatus in a microprocessor, the apparatus comprising: a reservation station to speculatively schedule and dispatch a first operation and also to speculatively determine a second operation is ready to be dispatched based on a speculated return of data at a predetermined time from the first operation, wherein the first operation is unable to return the data at the predetermined time; and a recovery mechanism to cancel the second operation and generate a bypass miss signal, provided the data from the first operation is not available at the predetermined time, wherein execution of the second operation is canceled if the second operation was dispatched, or wherein, in response to the bypass miss signal, the second operation is prevented from dispatching if the second operation has not been dispatched.
Claim 16
Independent Claim
128 words
An apparatus in a microprocessor, the apparatus comprising: a reservation station to speculatively schedule and dispatch a first operation and also to speculatively determine a second operation is ready to be dispatched based on a speculated return of data at a predetermined time from the first operation, wherein the first operation is unable to return the data at the predetermined time; and a recovery mechanism to cancel the second operation and generate a bypass miss signal, provided the data from the first operation is not available at the predetermined time, wherein execution of the second operation is canceled if the second operation was dispatched, or wherein, in response to the bypass miss signal, the second operation is prevented from dispatching if the second operation has not been dispatched.
Claim 17
Dependent Claim
27 words
The apparatus of claim 13, wherein the recovery mechanism comprises: circuitry to prevent an entry in the reservation station corresponding to the second operation from being deallocated.
Claim 18
Dependent Claim
33 words
The apparatus of claim 13, wherein the recovery mechanism comprises: circuitry, responsive to the bypass miss signal, to prevent a valid bit corresponding to the entry in the reservation station from being cleared.
Claim 19
Dependent Claim
24 words
The apparatus of claim 13, wherein the recovery mechanism comprises: circuitry to clear a physical destination address match indicator corresponding to the second operation.
Claim 20
Dependent Claim
45 words
The apparatus of claim 13, wherein the recovery mechanism is also to prevent a third operation from being dispatched from the reservation station, the third operation being ready for dispatch due to the speculated return of data at the predetermined time from the first operation.
Claim 21
Dependent Claim
137 words
A computer system comprising: a bus; and a processor coupled to the bus, wherein the processor includes, a reservation station to speculatively schedule and dispatch a first operation and also to speculatively determine a second operation is ready to be dispatched based on a speculated return of data at a predetermined time from the first operation, wherein the first operation is unable to return the data at the predetermined time; and a recovery mechanism to cancel the second operation and generate a bypass miss signal, provided the data from the first operation is not available at the predetermined time, wherein execution of the second operation is canceled if the second operation was dispatched, or wherein, in response to the bypass miss signal, the second operation is prevented from dispatching if the second operation has not been dispatched.
Claim 22
Dependent Claim
137 words
A computer system comprising: a bus; and a processor coupled to the bus, wherein the processor includes, a reservation station to speculatively schedule and dispatch a first operation and also to speculatively determine a second operation is ready to be dispatched based on a speculated return of data at a predetermined time from the first operation, wherein the first operation is unable to return the data at the predetermined time; and a recovery mechanism to cancel the second operation and generate a bypass miss signal, provided the data from the first operation is not available at the predetermined time, wherein execution of the second operation is canceled if the second operation was dispatched, or wherein, in response to the bypass miss signal, the second operation is prevented from dispatching if the second operation has not been dispatched.
Claim 23
Dependent Claim
27 words
The system of claim 18, wherein the recovery mechanism comprises: circuitry to prevent an entry in the reservation station corresponding to the second operation from being deallocated.
Claim 24
Dependent Claim
33 words
The system of claim 18, wherein the recovery mechanism comprises: circuitry, responsive to the bypass miss signal, to prevent a valid bit corresponding to the entry in the reservation station from being cleared.
Claim 25
Dependent Claim
24 words
The system of claim 18, wherein the recovery mechanism comprises: circuitry to clear a physical destination address match indicator corresponding to the second operation.
Claim 26
Dependent Claim
45 words
The system of claim 18, wherein the recovery mechanism is also to prevent a third operation from being dispatched from the reservation station, the third operation being ready for dispatch due to the speculated return of data at the predetermined time from the first operation.
Claim 27
Dependent Claim
109 words
In a processor, an apparatus for recovering an operation which has speculatively begun a series of stages for dispatching and executing the operation and which cannot be completed at a speculated time, the apparatus comprising: means for receiving a signal indicating that the operation cannot be completed at the speculated time; means for canceling execution of the operation in response to the receiving of the signal, if the operation has been dispatched; means for generating a bypass miss signal in response to the receiving of the signal; and means for preventing the operation from dispatching, in response to the bypass miss signal, if the operation has not been dispatched.
Claim 28
Dependent Claim
109 words
In a processor, an apparatus for recovering an operation which has speculatively begun a series of stages for dispatching and executing the operation and which cannot be completed at a speculated time, the apparatus comprising: means for receiving a signal indicating that the operation cannot be completed at the speculated time; means for canceling execution of the operation in response to the receiving of the signal, if the operation has been dispatched; means for generating a bypass miss signal in response to the receiving of the signal; and means for preventing the operation from dispatching, in response to the bypass miss signal, if the operation has not been dispatched.
Claim 29
Dependent Claim
23 words
The apparatus of claim 23, further comprising: means for preventing an entry of a reservation station, corresponding to the operation, from being deallocated.
Claim 30
Dependent Claim
32 words
The apparatus of claim 23, wherein the means for generating the bypass miss signal corresponds to a port of a reservation station from which the operation was or was to be dispatched.
Claim 31
Dependent Claim
38 words
The apparatus of claim 23, further comprising: means for preventing a second operation from being dispatched from a reservation station, the second operation being ready for dispatch due to a speculated return of data at the speculated time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |