Patent US5777671A successfully refreshed from Google Patents.
US5777671A
Expired / Lapsed
US
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Solid state imager having high frequency transfer mode
Assignee: Nikon Corp
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Filing: 1996-01-17
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Granted: 1998-07-07
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Expires: 2016-01-17
Abstract
Abstract A control circuit generates a control signal which is of a low level during a certain period of time after the power supply of a solid state imager has been turned on or a power save mode thereof has been canceled, and of a high level after elapse of the period of time. Based on the control signal, a timing generator generates transfer clock signals having a high frequency than when the solid state imager is in a normal transfer mode, and applies the transfer clock signals to a CCD shift register to remove or transfer excessive invalid charges at a high rate therefrom. After the power supply has been turned on or the power save mode has been canceled, therefore, the time required to bring the solid state imager into a condition capable of imaging a subject is shortened.
Inventors
- 👤 Yasuhito Maki
- 👤 Tetsuro Goto
- 👤 Tadao Takagi
- 👤 Hiroyuki Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:28
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/709; H04N25/701; H04N25/73
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
187 words
A solid state imager comprising: a solid state imaging section including: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a signal processor for processing said electric signals output from said charge detector; and a timing generator for generating a plurality of timing signals for directly driving said charge transfer section, said charge detector and said signal processor respectively, said timing signals including a first transfer clock signal for driving said charge transfer section at a first rate and a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, at least one of said timing signals other than said first and second transfer clock signals being fixed to a DC level in a transfer mode governed by said second transfer clock signal.
Claim 2
Dependent Claim
187 words
A solid state imager comprising: a solid state imaging section including: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a signal processor for processing said electric signals output from said charge detector; and a timing generator for generating a plurality of timing signals for directly driving said charge transfer section, said charge detector and said signal processor respectively, said timing signals including a first transfer clock signal for driving said charge transfer section at a first rate and a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, at least one of said timing signals other than said first and second transfer clock signals being fixed to a DC level in a transfer mode governed by said second transfer clock signal.
Claim 3
Dependent Claim
34 words
A solid state imager according to claim 1, wherein said plurality of timing signals includes reset pulses for performing resetting of said charge detector and said reset pulses are fixed to a DC level.
Claim 4
Dependent Claim
18 words
A solid state imager according to claim 1, wherein said reset pulses are fixed to a high level.
Claim 5
Dependent Claim
37 words
A solid state imager according to claim 1 further comprising: a signal processor connected to said charge detector for processing said signal voltages; said signal processor including a sample-and-hold circuit for sampling and holding said signal voltages.
Claim 6
Dependent Claim
36 words
A solid state imager according to claim 4, wherein said plurality of timing signals includes sample-and-hold pulses for performing sampling and holding of said charge signals and said sample-and-hold pulses are fixed to a DC level.
Claim 7
Dependent Claim
18 words
A solid state imager according to claim 4, wherein said sample-and-hold pulses are fixed to a high level.
Claim 8
Dependent Claim
22 words
A solid state imager according to claim 1 further comprising: a shift gate connected between said sensor and said charge transfer section.
Claim 9
Dependent Claim
45 words
A solid state imager according to claim 7, wherein said plurality of timing signals includes a read out gate pulse for reading said signal charges from said sensor into said charge transfer section and said read out gate pulse is fixed to a DC level.
Claim 10
Dependent Claim
20 words
A solid state imager according to claim 8, wherein said read out gate pulse is fixed to a low level.
Claim 11
Dependent Claim
147 words
A solid state imager, comprising: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a timing generator for generating a plurality of timing signals including a first transfer clock signal for driving said charge transfer section at a first rate, a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, and reset pulses for performing a reset operation of said charge detector, said reset pulses being fixed to a DC level in a transfer mode governed by said second transfer clock signal.
Claim 12
Dependent Claim
147 words
A solid state imager, comprising: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a timing generator for generating a plurality of timing signals including a first transfer clock signal for driving said charge transfer section at a first rate, a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, and reset pulses for performing a reset operation of said charge detector, said reset pulses being fixed to a DC level in a transfer mode governed by said second transfer clock signal.
Claim 13
Dependent Claim
18 words
A solid state imager according to claim 10, wherein said reset pulses are fixed to a high level.
Claim 14
Dependent Claim
37 words
A solid state imager according to claims 10 further comprising: a signal processor connected to said charge detector, for processing said electric signals; said signal processor including a sample-and-hold circuit for sampling and holding said electric signals.
Claim 15
Dependent Claim
47 words
A solid state imager according to claim 12, wherein said plurality of timing signals includes sample-and-hold pulses for performing sampling and holding of said electric signals and said sample-and-hold pulses are fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 16
Dependent Claim
18 words
A solid state imager according to claim 13, wherein said sample-and-hold pulses are fixed to a high level.
Claim 17
Dependent Claim
22 words
A solid state imager according to claim 10 further comprising: a shift gate connected between said sensor and said charge transfer section.
Claim 18
Dependent Claim
56 words
A solid state imager according to claim 15, wherein said plurality of timing signals includes a read out gate pulse for reading said signal charges from said sensor into said charge transfer section and said read out gate pulse is fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 19
Dependent Claim
20 words
A solid state imager according to claim 16, wherein said read out gate pulse is fixed to a low level.
Claim 20
Dependent Claim
175 words
A solid state imager comprising: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a signal processor connected to said charge detector for processing said electric signals, said signal processor including a sample-and-hold circuit for sampling and holding said electric signals; a timing generator for generating a plurality of timing signals including a first transfer clock signal for driving said charge transfer section at a first rate, a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, and sample-and-hold pulses for performing sampling and holding of said electric signals, and said sample-and-hold pulses are fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 21
Dependent Claim
175 words
A solid state imager comprising: a sensor having a plurality of pixels, said sensor comprising an at least linear array of photoelectric transducers representing said pixels, respectively; a charge transfer section for transferring signal charges read from the respective pixels of said sensor; a charge detector for detecting signal charges transferred by said charge transfer section, converting the detected signal charges into electric signals, and outputting the electric signals; a signal processor connected to said charge detector for processing said electric signals, said signal processor including a sample-and-hold circuit for sampling and holding said electric signals; a timing generator for generating a plurality of timing signals including a first transfer clock signal for driving said charge transfer section at a first rate, a second transfer clock signal for driving said charge transfer section at a second rate higher than said first rate, and sample-and-hold pulses for performing sampling and holding of said electric signals, and said sample-and-hold pulses are fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 22
Dependent Claim
18 words
A solid state imager according to claim 18, wherein said sample-and-hold pulses are fixed to a high level.
Claim 23
Dependent Claim
45 words
A solid state imager according to claim 18, wherein said plurality of timing signals includes reset pulses for performing resetting of said charge detector and said reset pulses are fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 24
Dependent Claim
18 words
A solid state imager according to claim 20, wherein said reset pulses are fixed to a high level.
Claim 25
Dependent Claim
22 words
A solid state imager according to claim 18 further comprising: a shift gate connected between said sensor and said charge transfer section.
Claim 26
Dependent Claim
56 words
A solid state imager according to claim 22, wherein said plurality of timing signals includes a read out gate pulse for reading said signal charges from said sensor into said charge transfer section and said read out gate pulse is fixed to a DC level in said transfer mode governed by said second transfer clock signal.
Claim 27
Dependent Claim
20 words
A solid state imager according to claim 23, wherein aid read out gate pulse is fixed to a low level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |