Parallel accumulator fractional-n frequency synthesizer

Claim 2

A frequency synthesizer, comprising: a synthesizer loop including a programmable divider; a divider control circuit providing a divider value to the programmable divider, the divider control circuit providing a variable divide value to the programmable divider for fractional division to produce a desired output frequency, and including a combining circuit and at least a first and second pulse generator connected in parallel; the first pulse generator including a first output for varying a first portion of the divide value to produce a first change in an average of the divide value; the second pulse generator including a second output for varying a second portion of the divide value to produce a second change in the average of the divide value; and the first and second outputs being combined and coupled to the programmable divider via the combining circuit.

Claim 3

The frequency synthesizer of claim 1, wherein the programmable divider is responsive to a fractional divide value, and wherein the first and second pulse generator outputs vary respective first and second portions of the fractional divide value.

Claim 4

The frequency synthesizer of claim 2, wherein the combining circuit adds an integer divide value with the fractional divide value to obtained an integer and fractional divide value, and applies the integer and fractional divide value to the programmable divider.

Claim 5

The frequency synthesizer of claim 1, wherein the pulse generators are selected from at least one of the group consisting of pulse generators with pseudo-random properties, accumulators, fractional-N cascaded multi-accumulators, fractional-N sigma-delta cascaded multi-accumulators, and microprocessors.

Claim 6

The frequency synthesizer of claim 4, wherein the pulse generators are accumulators having respective first and second inputs for receiving data.

Claim 7

The frequency synthesizer of claim 5, wherein the accumulators have the same lengths with each accumulator being driven by different clock frequencies.

Claim 8

The frequency synthesizer of claim 5, wherein the accumulators have different accumulator lengths.

Claim 9

The frequency synthesizer of claim 5, wherein the first and second outputs are respective carries of the first and second accumulators.

Claim 10

The frequency synthesizer of claim 8, wherein the carries are summed in the combining circuit.

Claim 11

The frequency synthesizer of claim 8, wherein the combining circuit includes a multiplexer which multiplexes the carries of the accumulators, a control signal for the multiplexer being coupled from an output of the programmable divider, a clock frequency is derived from an output of the programmable divider and applied to clock inputs of the at least first and second accumulators.

Claim 12

A high resolution frequency synthesizer, comprising: a synthesizer loop including a programmable fractional-N divider; a divider control circuit providing a divider value to the programmable divider, the divider control circuit providing a variable divide value to the programmable divider for fractional division to produce a desired output frequency, and including a combining circuit and at least a first and second accumulator connected in parallel; the first accumulator having a first accumulator length and including a clock input, a first input for receiving data and a first output for increasing a first portion of the fractional divide value to produce a first change in an average of the fractional divide value; the second accumulator having a second accumulator length different from the first accumulator length and including a clock input, a second input for receiving data and a second output for decreasing a second portion of the fractional divide value to produce a second change in the average of the fractional divide value; and the first and second outputs being combined and coupled to the programmable divider via the combining circuit to produce a combined change in the average of the fractional divide value.

Claim 13

A high resolution frequency synthesizer, comprising: a synthesizer loop including a programmable fractional-N divider; a divider control circuit providing a divider value to the programmable divider, the divider control circuit providing a variable divide value to the programmable divider for fractional division to produce a desired output frequency, and including a combining circuit and at least a first and second accumulator connected in parallel; the first accumulator having a first accumulator length and including a clock input, a first input for receiving data and a first output for increasing a first portion of the fractional divide value to produce a first change in an average of the fractional divide value; the second accumulator having a second accumulator length different from the first accumulator length and including a clock input, a second input for receiving data and a second output for decreasing a second portion of the fractional divide value to produce a second change in the average of the fractional divide value; and the first and second outputs being combined and coupled to the programmable divider via the combining circuit to produce a combined change in the average of the fractional divide value.

Claim 14

The frequency synthesizer of claim 11, wherein the combining circuit adds an integer divide value with the fractional divide value to obtained an integer and fractional divide value, and applies the integer and fractional divide value to the programmable divider.

Claim 15

The frequency synthesizer of claim 11, wherein the first and second outputs are respective carries of the first and second accumulators, the carries being combined in the combining circuit.

Claim 16

The frequency synthesizer of claim 11, wherein the combining circuit includes a multiplexer which multiplexes the outputs of the accumulators, a control signal for the multiplexer being coupled from an output of the programmable divider, a clock frequency is derived from an output of the programmable divider and is divided by at least the total number of accumulators and applied to the clock inputs of the at least first and second accumulators.

Claim 17

A radio communication device having at least one of a transmitter and a receiver and having a frequency synthesizer, comprising: a synthesizer loop including a programmable divider; a divider control circuit providing a divider value to the programmable divider, the divider control circuit providing a variable divide value to the programmable divider for fractional division to produce a desired output frequency, and including a combining circuit and at least a first and second accumulator; the first accumulator including a first input for receiving data and a first output for varying a first portion of the divide value to produce a first change in an average of the divide value; the second accumulator including a second input for receiving data and a second output for varying a second portion of the divide value to produce a second change in the average of the divide value; and the first and second outputs being combined and coupled to the programmable divider via the combining circuit.

Claim 18

A radio communication device having at least one of a transmitter and a receiver and having a frequency synthesizer, comprising: a synthesizer loop including a programmable divider; a divider control circuit providing a divider value to the programmable divider, the divider control circuit providing a variable divide value to the programmable divider for fractional division to produce a desired output frequency, and including a combining circuit and at least a first and second accumulator; the first accumulator including a first input for receiving data and a first output for varying a first portion of the divide value to produce a first change in an average of the divide value; the second accumulator including a second input for receiving data and a second output for varying a second portion of the divide value to produce a second change in the average of the divide value; and the first and second outputs being combined and coupled to the programmable divider via the combining circuit.

Claim 19

The radio communication device of claim 15, wherein the frequency synthesizer includes accumulators having different accumulator lengths, and wherein the frequency synthesizer includes the programmable divider being responsive to a fractional divide value, and wherein the first and second accumulator outputs vary respective first and second portions of the fractional divide value.

Claim 20

The radio communication device of claim 16, wherein the frequency synthesizer combining circuit adds an integer divide value with the fractional divide value to obtained an integer and fractional divide value, and applies the integer and fractional divide value to the programmable divider.

Claim 21

The radio communication device of claim 16, wherein the first and second outputs are respective carries of the first and second accumulators, the carries being summed in the combining circuit.

Claim 22

The radio communication device of claim 16, wherein the frequency synthesizer combining circuit includes a multiplexer which multiplexes the outputs of the accumulators, a control signal for the multiplexer being coupled from an output of the programmable divider, a clock frequency is derived from an output of the programmable divider and applied to clock inputs of the at least first and second accumulators.

Claim 25

The method of claim 20, wherein the providing step includes the divider being responsive to the fractional divide value, and wherein the inputting step includes the respective accumulator outputs being responsive to associated portions of the fractional divide value.

Claim 26

The method of claim 20, wherein the combining step includes combining an integer divide value with the fractional divide value to obtained a summed integer and fractional divide value, and wherein the applying step includes applying the summed integer and fractional divide value to the divider.

Claim 27

The method of claim 22, wherein the providing step includes the combining circuit having a multiplexer which multiplexes the outputs of the accumulators, a control signal for the multiplexer being coupled from an output of the programmable divider.