US3872397A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for decreasing channel spacing in digital frequency synthesizers
Assignee: King Radio Corp
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Filing: 1973-11-07
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Granted: 1975-03-18
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Expires: 1993-11-07
Abstract
Abstract A method and apparatus for digital frequency synthesis is provided which enables the channel spacing of a digital synthesizer to be decreased below a reference frequency. The frequency clock output of a voltage controlled oscillator is digitally divided by an average multiple which may be other than a whole number. The output of the divider forms the input to a digital phase comparator which compares the phase of the reference frequency and the input or feedback frequency and generates a signal output that has a duty cycle proportional to the phase difference between the reference and feedback frequencies. The last mentioned output signal eventually is used to bias the voltage controlled oscillator to the proper output frequency so that the feedback and reference frequencies have a constant phase difference. Since the average multiple of the divider can be varied fractionally, a plurality of output signals from the voltage controlled oscillator are obtainable which have frequency spacing between them of some frequency less than the reference frequency.
Inventors
- 👤 Charles K Hanneman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:53
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
174 words
In a frequency synthesizer having a phase locked loop including a phase comparator that receives a reference frequency and compares it to a feedback frequency, delivers an output signal based on that comparison, and has a voltage controlled oscillator providing a frequency output based on the output of said phase comparator, and a digital divider electrically connected between said voltage controlled oscillator and said phase comparator for providing said feedback signal to said comparator, the improvement comprising means for causing the digital divider to either divide by the divide ratios N or N'' thereby yielding an average ratio of N1 + N2 + . . . NN + N''1 + N''2 + ... N''MN'''' wherein N1 through NN, N''1 through N''M and N'''' are integers and N'''' equals M + N, said last mentioned means comprising means for changing said divide ratios N to N'', and means for averaging the divide ratios N and N'' by dividing the sum of N1 + N2 . . . NN + N''1 + ... N''M by N''''.
Claim 2
Dependent Claim
174 words
In a frequency synthesizer having a phase locked loop including a phase comparator that receives a reference frequency and compares it to a feedback frequency, delivers an output signal based on that comparison, and has a voltage controlled oscillator providing a frequency output based on the output of said phase comparator, and a digital divider electrically connected between said voltage controlled oscillator and said phase comparator for providing said feedback signal to said comparator, the improvement comprising means for causing the digital divider to either divide by the divide ratios N or N'' thereby yielding an average ratio of N1 + N2 + . . . NN + N''1 + N''2 + ... N''MN'''' wherein N1 through NN, N''1 through N''M and N'''' are integers and N'''' equals M + N, said last mentioned means comprising means for changing said divide ratios N to N'', and means for averaging the divide ratios N and N'' by dividing the sum of N1 + N2 . . . NN + N''1 + ... N''M by N''''.
Claim 3
Dependent Claim
79 words
The improvement as in claim 1 wherein said changing means includes inhibit means electrically connected to the input side of said divider, and inhibit control means for actuating said inhibit means, said inhibit control means connected between the output side of said divider and said inhibit means, said inhibit control means being selectively programmable to cause said inhibit means to vary the division ratio of said divider by inhibiting input signals to said divider according to a preselected schedule.
Claim 4
Dependent Claim
18 words
The improvement of claim 2 wherein said digital divider comprises a plurality of cascaded synchronous digital counter stages.
Claim 5
Dependent Claim
27 words
The improvement of claim 3 wherein said inhibit means comprises a first flip-flop electrically connected to the first stage of a three stage cascaded synchronous digital counter.
Claim 6
Dependent Claim
58 words
The improvement of claim 4 wherein said inhibit control means comprises a second flip-flop electrically connected to the output side of said divider, a third flip-flop having an output side electrically connected to said second flip-flop, and an NAND gate electrically connected between the output side of said second flip-flop and an input side of said first flip-flop.
Claim 7
Independent Claim
105 words
A method of digital frequency synthesis, comprising: presetting a digital divider N states away from a load state; feeding output pulses from a frequency generating means to said digital divider; providing an output pulse from said digital divider when the number of pulses from said frequency generating means equals N; inhibiting a preselected number of pulses to said digital divider after a preselected number of output pulses from said digital divider; enabling said digital divider after said preselected number of pulses are inhibited; and providing a succeeding output pulse from said digital divider when the number of pulses from said frequenCy generating means equals N.
Claim 8
Independent Claim
105 words
A method of digital frequency synthesis, comprising: presetting a digital divider N states away from a load state; feeding output pulses from a frequency generating means to said digital divider; providing an output pulse from said digital divider when the number of pulses from said frequency generating means equals N; inhibiting a preselected number of pulses to said digital divider after a preselected number of output pulses from said digital divider; enabling said digital divider after said preselected number of pulses are inhibited; and providing a succeeding output pulse from said digital divider when the number of pulses from said frequenCy generating means equals N.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-17 | 1978-09-16 | 1979-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-17 | 1982-09-16 | 1983-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-17 | 1986-09-16 | 1987-03-18 | $7700.00 | Window Closed / Lapsed |