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US5776829A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming multilevel interconnections in a semiconductor device

Assignee: NEC Corp
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Filing: 1995-11-22
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Granted: 1998-07-07
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Expires: 2015-11-22
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Abstract

Abstract The present invention provides a novel method for forming multilevel interconnections in a semiconductor device. A silicon oxide film is formed on a semiconductor substrate. A first photo-resist film pattern is formed on the first silicon oxide film. The surface of the silicon oxide film covered with the photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film by use of the first photo-resist film pattern as a mask. The first photo-resist film pattern is removed, thereby resulting in first grooves in the fluoro-containing silicon oxide film. First interconnections are formed within the first grooves. An inter-layer insulator is formed on an entire surface of the device and then subjected to a dry etching and a photolithography to form via holes in the inter-layer insulator. Conductive films are selectively formed in the via holes. A second photo-resist film pattern is selectively formed to cover the conductive films within the via holes. The entire surface of the device covered with the second photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the inter-layer insulator by use of the second photo-resist film pattern as a mask. The second photo-resist film pattern is removed, thereby resulting in second grooves in the second fluoro-containing silicon oxide film. Second interconnections are formed within the second grooves.

Inventors

  • 👤 Tetsuya Homma
  • 👤 Makoto Sekine

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 01:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 505 words
A method for forming multilevel interconnections in a semiconductor device, comprising the sequential steps of: forming a first silicon oxide film on a semiconductor substrate; forming a first photo-resist film pattern on the first silicon oxide film; exposing the surface of the silicon oxide film not covered with the photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film using the first photo-resist film pattern as a mask; removing the first photo-resist film pattern to form first grooves in the fluoro-containing silicon oxide film; forming a first metal film extending within said first grooves and over said first fluoro-containing silicon oxide film; subjecting said first metal film to a first chemical and mechanical polishing to leave said metal film only within said first grooves so that a remaining first metal film has a top surface at a same level as a top surface of said first fluoro-containing silicon oxide film to form a first flat top surface of said substrate; forming a second silicon oxide film on the first flat top surface of device; said substrate; selectively forming a second photo-resist film pattern on said second silicon oxide film; exposing an entire surface of the device covered with the second photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the second silicon oxide film using the second photo-resist film pattern as a mask; removing the second photo-resist film pattern to form second grooves in the second fluoro-containing silicon oxide film; removing the second silicon oxide film from within the second grooves; forming a second metal film extending within said second grooves and over said second fluoro-containing silicon oxide film; subjecting said second metal film to a second chemical and mechanical polishing to leave said second metal film only within said second grooves so that a remaining second metal film has a top surface at a same level as a top surface of said second fluoro-containing silicon oxide film to form a second flat top surface of said substrate; selectively forming a third photo-resist film pattern on said second fluoro-containing silicon oxide film; exposing an entire surface of the device covered with the third photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a third fluoro-containing silicon oxide film on the second fluoro-containing silicon oxide film using the third photoresist film pattern as a mask; removing the third photo-resist film pattern to form third grooves in the third fluoro-containing silicon oxide film; forming a third metal film extending within said third grooves and over said third fluoro-containing silicon oxide film; and subjecting said third metal film to a third chemical and mechanical polishing to leave said third metal film only within said third grooves so that a remaining third metal film has a top surface at a same level as a top surface of said third fluoro-containing silicon oxide film to form a third flat top surface of said substrate.
Claim 2
Independent Claim 505 words
A method for forming multilevel interconnections in a semiconductor device, comprising the sequential steps of: forming a first silicon oxide film on a semiconductor substrate; forming a first photo-resist film pattern on the first silicon oxide film; exposing the surface of the silicon oxide film not covered with the photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film using the first photo-resist film pattern as a mask; removing the first photo-resist film pattern to form first grooves in the fluoro-containing silicon oxide film; forming a first metal film extending within said first grooves and over said first fluoro-containing silicon oxide film; subjecting said first metal film to a first chemical and mechanical polishing to leave said metal film only within said first grooves so that a remaining first metal film has a top surface at a same level as a top surface of said first fluoro-containing silicon oxide film to form a first flat top surface of said substrate; forming a second silicon oxide film on the first flat top surface of device; said substrate; selectively forming a second photo-resist film pattern on said second silicon oxide film; exposing an entire surface of the device covered with the second photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the second silicon oxide film using the second photo-resist film pattern as a mask; removing the second photo-resist film pattern to form second grooves in the second fluoro-containing silicon oxide film; removing the second silicon oxide film from within the second grooves; forming a second metal film extending within said second grooves and over said second fluoro-containing silicon oxide film; subjecting said second metal film to a second chemical and mechanical polishing to leave said second metal film only within said second grooves so that a remaining second metal film has a top surface at a same level as a top surface of said second fluoro-containing silicon oxide film to form a second flat top surface of said substrate; selectively forming a third photo-resist film pattern on said second fluoro-containing silicon oxide film; exposing an entire surface of the device covered with the third photo-resist film pattern to a super-saturated hydrosilicofluoric acid solution to selectively deposit a third fluoro-containing silicon oxide film on the second fluoro-containing silicon oxide film using the third photoresist film pattern as a mask; removing the third photo-resist film pattern to form third grooves in the third fluoro-containing silicon oxide film; forming a third metal film extending within said third grooves and over said third fluoro-containing silicon oxide film; and subjecting said third metal film to a third chemical and mechanical polishing to leave said third metal film only within said third grooves so that a remaining third metal film has a top surface at a same level as a top surface of said third fluoro-containing silicon oxide film to form a third flat top surface of said substrate.
Claim 3
Dependent Claim 54 words
The method as claimed in claim 1, wherein during the steps of forming of the first, second and third fluoro-containing silicon oxide films, the hydrosilicofluoric acid solution is maintained at a temperature of 35° C. so that the solubility of aluminum to 1 liter of hydrosilicofluoric acid solution is set at approximately 0.5 g/hour.
Claim 4
Dependent Claim 36 words
The method as claimed in claim 1, further comprising the step of: forming a base film mainly containing silicon oxide on the entire surface of the device prior to the formation of the second photo-resist film.
Claim 5
Dependent Claim 138 words
The method as claimed in claim 1, wherein the step for forming the first, second, and third metal films comprises the following steps of: forming a titanium film on an entire surface of the device by sputtering; forming a titanium nitride film on the titanium film by sputtering; forming an aluminum film on the titanium nitride film by a thermal chemical vapor phase deposition carried out by the following steps of: vaporizing dimethylaluminumhydride AlH(CH 3 ) 2 by a bubbling method with a carrier gas of hydrogen at a temperature of 30° C.; and introducing the vaporized dimethylaluminumhydride AlH(CH 3 ) 2 into a reaction chamber, where a flow rate of hydrogen gas is controlled at 250 sccm, a temperature of the substrate is maintained at 250° C. and a pressure of the reaction chamber is 130 Pa.

References Cited (Backward Citations)

US5328873A Cited
US5304510A Cited
US5326720A Cited
JPH06216128A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-07-06 2002-01-05 2002-07-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-07-06 2006-01-05 2006-07-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-07-06 2010-01-05 2010-07-07 $7700.00 Window Closed / Lapsed

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