Patent US5774711A successfully refreshed from Google Patents.
US5774711A
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Apparatus and method for processing exceptions during execution of string instructions
Assignee: IP First LLC
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Filing: 1996-07-26
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Granted: 1998-06-30
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Expires: 2016-07-26
Abstract
Abstract An apparatus and method for handling exceptions during execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation, and an execution unit for executing the micro instruction sequence. A counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is incremented/decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from the counter which indicates that all of the string has been operated upon, e.g., if the counter reaches zero. If exceptions occur during the operation of the translator generated string instructions, the value of the counter is stored in a temporary register, the string operation is ended as if the counter reached zero, the exception is handled, the value of the counter is restored, and the string operation is restarted.
Inventors
- 👤 Glenn Henry
- 👤 Terry Parks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/30003; G06F9/30007; G06F9/30032
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
253 words
A processing system for executing a string instruction, and for handling exceptions during the execution of the string instruction, the processing system comprising: a memory system, for storing a string of data; a translator, for decoding said string instruction into a repetitive sequence of micro instructions for operation upon said string of data, said repetitive sequence not containing a branch instruction for the purpose of repetition; an execution unit, coupled to said translator, for executing said repetitive sequence of micro instructions, wherein said execution unit detects whether micro instructions which it executes are associated with said string instruction; a counter coupled to said translator and to said execution unit, for storing a count value indicative of the number of times said repetitive sequence needs to be executed to operate on all of said string of data, for counting the number of times said execution unit has executed said repetitive sequence of micro instructions; and for providing a first signal to said translator when all of said string of data has been operated upon; a register, coupled to said counter, for temporarily storing count information during handling of said exceptions; and exception logic, coupled to said translator, for interrupting said execution of said repetitive sequence of micro instructions with a second signal upon the occurrence of an exception; whereby said second signal causes said processing system to transfer said count information to said register, to handle said exceptions, to transfer said count information to said counter, and to resume execution of said string instruction.
Claim 2
Dependent Claim
253 words
A processing system for executing a string instruction, and for handling exceptions during the execution of the string instruction, the processing system comprising: a memory system, for storing a string of data; a translator, for decoding said string instruction into a repetitive sequence of micro instructions for operation upon said string of data, said repetitive sequence not containing a branch instruction for the purpose of repetition; an execution unit, coupled to said translator, for executing said repetitive sequence of micro instructions, wherein said execution unit detects whether micro instructions which it executes are associated with said string instruction; a counter coupled to said translator and to said execution unit, for storing a count value indicative of the number of times said repetitive sequence needs to be executed to operate on all of said string of data, for counting the number of times said execution unit has executed said repetitive sequence of micro instructions; and for providing a first signal to said translator when all of said string of data has been operated upon; a register, coupled to said counter, for temporarily storing count information during handling of said exceptions; and exception logic, coupled to said translator, for interrupting said execution of said repetitive sequence of micro instructions with a second signal upon the occurrence of an exception; whereby said second signal causes said processing system to transfer said count information to said register, to handle said exceptions, to transfer said count information to said counter, and to resume execution of said string instruction.
Claim 3
Dependent Claim
21 words
The processing system, as recited in claim 1, wherein said memory system comprises cache memory, dynamic-random-access memory, or permanent storage memory.
Claim 4
Dependent Claim
27 words
The processing system, as recited in claim 1, wherein said string of data comprises a plurality of bytes of data stored in sequential locations in said memory.
Claim 5
Dependent Claim
24 words
The processing system, as recited in claim 1, wherein said translator further comprises: a control ROM, for storing exception programs for handling said exceptions.
Claim 6
Dependent Claim
23 words
The processing system, as recited in claim 4 wherein said control ROM also stores non repetitive micro instructions associated with said string instruction.
Claim 7
Dependent Claim
33 words
The processing system, as recited in claim 5 wherein said control ROM provides said non repetitive sequence to said execution unit upon said translator receiving either of said first or said second signals.
Claim 8
Dependent Claim
32 words
The processing system, as recited in claim 1, wherein said repetitive sequence of micro instructions is provided continuously by said translator until either said first signal or said second signal is received.
Claim 9
Dependent Claim
31 words
The processing system, as recited in claim 7, wherein when said first signal is received by said translator, said count information having a value of zero is stored in said register.
Claim 10
Dependent Claim
33 words
The processing system, as recited in claim 7, wherein when said second signal is received by said translator, said count information having a value that is not zero is stored in said register.
Claim 11
Dependent Claim
40 words
The processing system, as recited in claim 9, wherein when said second signal is received by said translator, after handling said exception, said count information having a value that is not zero is transferred from said register to said counter.
Claim 12
Dependent Claim
24 words
The processing system, as recited in claim 10, wherein said translator begins generating said repetitive sequence of micro instructions upon returning from said exception.
Claim 13
Dependent Claim
26 words
The processing system, as recited in claim 1, wherein said counter comprises a temporary register which counts down towards zero during execution of said repetitive sequence.
Claim 14
Dependent Claim
221 words
A processing system having a translator for generating a repetitive sequence of first micro instructions related to a string instruction, a control ROM for providing second micro instructions to complete the string instruction and for storing exception routines, an execution unit for executing the first and second micro instructions and the exception routines, the processing system comprising: an instruction pointer, for pointing to a first macro instruction; a next instruction pointer, for pointing to a second macro instruction; control logic, connected to both of said instruction pointer and said next instruction pointer, for selecting between said first or said second macro instruction to be returned to after an exception; and exception logic for interrupting the execution unit with either a fault or a trap; wherein when said exception logic interrupts the execution unit with either a trap or a fault, if the processing system was executing the repetitive sequence of first micro instructions at the time of the interrupt, said control logic selects said first macro instruction to be returned to after said fault or trap; and wherein if the processing was not executing the repetitive sequence of first micro instructions at the time of the interrupt, and if the interrupt was a trap, said control logic selects said second macro instruction to be returned to after said fault or trap.
Claim 15
Dependent Claim
221 words
A processing system having a translator for generating a repetitive sequence of first micro instructions related to a string instruction, a control ROM for providing second micro instructions to complete the string instruction and for storing exception routines, an execution unit for executing the first and second micro instructions and the exception routines, the processing system comprising: an instruction pointer, for pointing to a first macro instruction; a next instruction pointer, for pointing to a second macro instruction; control logic, connected to both of said instruction pointer and said next instruction pointer, for selecting between said first or said second macro instruction to be returned to after an exception; and exception logic for interrupting the execution unit with either a fault or a trap; wherein when said exception logic interrupts the execution unit with either a trap or a fault, if the processing system was executing the repetitive sequence of first micro instructions at the time of the interrupt, said control logic selects said first macro instruction to be returned to after said fault or trap; and wherein if the processing was not executing the repetitive sequence of first micro instructions at the time of the interrupt, and if the interrupt was a trap, said control logic selects said second macro instruction to be returned to after said fault or trap.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |