Equalization and decoding for digital communication channel

Claim 3

The method as set forth in claim 1 wherein said utilizing step further includes the step of using a Viterbi algorithm.

Claim 4

The method as set forth in claim 1 wherein a particular candidate symbol sequence includes a plurality of candidate symbols and said utilizing step further includes the step of generating a current value for a currently received symbol of said particular candidate symbol sequence, said current value affected by intersymbol interference caused by at least one symbol transmitted through said communications channel prior to said current symbol.

Claim 5

The method as set forth in claim 3 wherein said generating step further includes the step of using at least one of a first prior value determined for a symbol received at a time k-1 and at least a second prior value determined for a symbol received at a time k to generate said current value for said currently received symbol where said currently received symbol is received at a time k+1.

Claim 6

The method as set forth in claim 4 wherein said first prior value is associated with a particular candidate symbol sequence yielding the minimum value for said error signal at said time k.

Claim 7

The method as set forth in claim 5 further including the step of using the minimum value for said error signal to update at least a portion of said multi-state trellis, the updated portion of said multi-state trellis being updated to include new symbol states.

Claim 8

The method as set forth in claim 1 wherein said utilizing step further includes the step of determining the minimum-distance path through said multi-state trellis.

Claim 9

The method as set forth in claim 1 further including the step of updating at least a portion of said multi-state trellis using the minimum value for said error signal, the updated portions of said multi-state trellis being updated to include new symbol states each new symbol state of said multi-state trellis corresponding to a respective minimum value of said error signal.

Claim 10

The method as set forth in claim 1 wherein said utilizing step further includes the step of storing at least one candidate symbol of at least one candidate symbol sequence.

Claim 11

The method as set forth in claim 9 wherein said utilizing step further includes the step of using said one or more stored candidate symbols to generate one or more values for a particular candidate symbol sequence.

Claim 12

A decoder for decoding a received time varying signal, said time varying signal representing a sequence of symbols that were transmitted through a communications channel, said sequence of symbols having been transmitted at a symbol rate, said circuit comprising: a memory operative to store a multi-state trellis, said multi-state trellis representing a plurality of possible state changes for said time varying signal; and a circuit operative to: sample said time varying signal to generate a set of R sample d values, said time varying signal being sampled at a sampling rate of R/T wherein R≧2; utilize said multi-state trellis to generate a set of estimated values for each one of a set of candidate symbol sequences; compare ones of said set of R sample d values with corresponding ones of said set of estimated values for each of said candidate symbol sequences to form an error signal; and select the candidate symbol sequence yielding the minimum value for said error signal as a decoded version of the sequence of symbols transmitted through said communications channel.

Claim 13

A decoder for decoding a received time varying signal, said time varying signal representing a sequence of symbols that were transmitted through a communications channel, said sequence of symbols having been transmitted at a symbol rate, said circuit comprising: a memory operative to store a multi-state trellis, said multi-state trellis representing a plurality of possible state changes for said time varying signal; and a circuit operative to: sample said time varying signal to generate a set of R sample d values, said time varying signal being sampled at a sampling rate of R/T wherein R≧2; utilize said multi-state trellis to generate a set of estimated values for each one of a set of candidate symbol sequences; compare ones of said set of R sample d values with corresponding ones of said set of estimated values for each of said candidate symbol sequences to form an error signal; and select the candidate symbol sequence yielding the minimum value for said error signal as a decoded version of the sequence of symbols transmitted through said communications channel.

Claim 14

The decoder as set forth in claim 11 wherein said circuit is operative to execute a Viterbi algorithm.

Claim 15

The decoder as set forth in claim 11 wherein a particular candidate symbol sequence includes a plurality of candidate symbols and said circuit is further operative to generate a current value for a currently received symbol of said particular candidate symbol sequence, said current value affected by intersymbol interference caused by at least one symbol supplied to said communications channel prior to said currently received symbol.

Claim 16

The decoder as set forth in claim 13 wherein said circuit is further operative to use at least one of a first prior value determined for a symbol received at a time k-1 and at least a second prior value determined for a symbol received at a time k to generate said current value for said currently received symbol where said currently received symbol is received at a time k+1.

Claim 17

The decoder as set forth in claim 14 wherein said first prior value is associated with a particular candidate symbol sequence yielding the minimum value for said error signal at said time k.

Claim 18

The decoder as set forth in claim 15 wherein said circuit is further operative to use the minimum value for said error signal to update at least a portion of said multi-state trellis, the updated portion of said multi-state trellis being updated to include new symbol states.

Claim 19

The decoder as set forth in claim 11 wherein said circuit is further operative to determine the minimum-distance path through said multi-state trellis.

Claim 20

The decoder as set forth in claim 11 wherein said circuit is further operative to update at least a portion of said multi-state trellis using the minimum value for said error signal, the updated portions of said multi-state trellis being updated to include new symbol states, each new symbol state of said multi-state trellis corresponding to a respective minimum value of said error signal.

Claim 21

The decoder as set forth in claim 11 wherein said circuit is further operative to store at least one candidate symbol of at least one candidate symbol sequence.

Claim 22

The decoder as set forth in claim 11 wherein said circuit is further operative to use said one or more stored candidate symbols to generate one or more values for a particular candidate symbol sequence.

Claim 23

The method as set forth in claim 1 wherein a particular candidate sequence includes a plurality of candidate symbols and said utilizing step further includes the step of generating a current value for a currently received symbol of said particular candidate symbol sequence.

Claim 24

The method as set forth in claim 1 wherein a particular candidate sequence includes a plurality of candidate symbols and said utilizing step further includes the step of generating a current value for a currently received symbol of said particular candidate symbol sequence, said current value being affected by intersymbol interference.

Claim 27

The method of claim 23 wherein each corresponding subchannel has a respective estimated channel characteristic.

Claim 28

The method of claim 23 further comprising the steps of: computing a combined error value derived from said step of comparing the R subsequences and utilizing the combined error value to make an interim decision about the sequence of symbols.

Claim 29

The method of claim 23 further comprising the step of computing a combined error value derived from said step of comparing the R subsequences and utilizing the combined error value to make a final decision about the sequence of symbols.

Claim 30

The method of claim 25 further comprising the step of utilizing the combined error value and the interim decision to make a final decision about the sequence of symbols.

Claim 31

The method of claim 23 further comprising the step of employing a channel impulse response tracking algorithm including an update algorithm based on more than one locally best estimate.

Claim 32

The method of claim 28 wherein each locally best estimate comprises R subchannel estimates.

Claim 33

The method of claim 29 further comprising the step of utilizing the R subchannel estimates with a modified Viterbi algorithm.

Claim 34

The method of claim 24 further comprising the step of utilizing a leaky channel predictor for estimating channel characteristics on an ongoing basis.

Claim 35

The method of claim 23 further comprising the step of utilizing a plurality of receiver antennas to generate the time varying baseband signal and one or more additional time varying baseband signals.

Claim 36

A decoder for decoding a time varying baseband signal which was received from a communications channel, said time varying baseband signal representing a sequence of symbols that was transmitted through the communications channel at a transmitted symbol repetition rate of 1/T, said circuit comprising: a memory operative to store a multi-state trellis, said multi-state trellis representing a plurality of possible state changes for said time varying signal; and a circuit operative to: sample said time varying baseband signal at a sampling rate equal to an R, R≧2, multiple of the transmitted symbol repetition rate; decimate the resulting sampled sequence in time to produce R subsequences, each having a sample rate of 1/T; utilize said multi-state trellis to generate a set of local values for each one of the R subsequences, the set of local values representing the result of the passage of a current symbol and a predetermined number of past symbols through corresponding subchannels of said communications channel; and compare ones of said set of local values with ones of the R subsequences.

Claim 37

A decoder for decoding a time varying baseband signal which was received from a communications channel, said time varying baseband signal representing a sequence of symbols that was transmitted through the communications channel at a transmitted symbol repetition rate of 1/T, said circuit comprising: a memory operative to store a multi-state trellis, said multi-state trellis representing a plurality of possible state changes for said time varying signal; and a circuit operative to: sample said time varying baseband signal at a sampling rate equal to an R, R≧2, multiple of the transmitted symbol repetition rate; decimate the resulting sampled sequence in time to produce R subsequences, each having a sample rate of 1/T; utilize said multi-state trellis to generate a set of local values for each one of the R subsequences, the set of local values representing the result of the passage of a current symbol and a predetermined number of past symbols through corresponding subchannels of said communications channel; and compare ones of said set of local values with ones of the R subsequences.

Claim 38

The decoder of claim 33 wherein the circuit further operates to compute a combined error value derived from said comparing of local values and R subsequences, and to make an interim decision about the symbols and the sequence.

Claim 39

The decoder of claim 33 wherein the circuit further operates to compute a combined error value derived from said comparing of local values and R subsequences, and to make a final decision about the symbols and the sequence.

Claim 40

The decoder of claim 33 wherein the circuit employs a channel impulse tracking algorithm.

Claim 41

The decoder of claim 33 further comprising a leaky channel predictor for estimating channel characteristics on an ongoing basis.