US5774400A
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Structure and method to prevent over erasure of nonvolatile memory transistors
Assignee: NVX Corp
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Filing: 1996-12-23
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Granted: 1998-06-30
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Expires: 2016-12-23
Abstract
Abstract A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.
Inventors
- 👤 Loren T. Lancaster
- 👤 Ryan T. Hirose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3477; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
126 words
A non-volatile integrated memory device, comprising: a semiconductor substrate; a memory transistor in said substrate, said memory transistor having an electrically alterable threshold voltage, said memory transistor having a source region, a drain region, a channel region between said source and drain regions in said substrate, a gate, and a charge storage layer between at least portions of said gate and said substrate; means for simultaneously injecting charge into said charge storage layer from at least a first node and a second node during a write operation in which the threshold voltage of said memory transistor is charged; and means for setting current flows from said first and second nodes to be substantially equal in magnitude when a predetermined value is achieved during the write operation.
Claim 2
Dependent Claim
126 words
A non-volatile integrated memory device, comprising: a semiconductor substrate; a memory transistor in said substrate, said memory transistor having an electrically alterable threshold voltage, said memory transistor having a source region, a drain region, a channel region between said source and drain regions in said substrate, a gate, and a charge storage layer between at least portions of said gate and said substrate; means for simultaneously injecting charge into said charge storage layer from at least a first node and a second node during a write operation in which the threshold voltage of said memory transistor is charged; and means for setting current flows from said first and second nodes to be substantially equal in magnitude when a predetermined value is achieved during the write operation.
Claim 3
Dependent Claim
19 words
The device according to claim 1 wherein at least one of said nodes provides current by quantum mechanical tunneling.
Claim 4
Dependent Claim
56 words
The device according to claim 1 wherein said means for setting the current flow from said nodes comprises at least means for controlling an externally applied voltage to create an electric field and the electric field created by the accumulated charge in said charge storage layer to control the current from said first and second nodes.
Claim 5
Dependent Claim
43 words
The device according to claim 3 wherein said means to set current flow further comprises means for decreasing the magnitude of current from said first node and to simultaneously increase the magnitude of current from said second node as said accumulated charge increases.
Claim 6
Dependent Claim
19 words
The device according to claim 3 wherein said externally applied voltage is applied between said gate and said substrate.
Claim 7
Dependent Claim
15 words
The device according to claim 1 wherein said first node comprises said memory transistor channel.
Claim 8
Dependent Claim
15 words
The device according to claim 1 wherein said second node comprises said memory transistor gate.
Claim 9
Dependent Claim
33 words
The device according to claim 1 further comprising a bottom tunnel oxide between said substrate and said charge storage layer and a top blocking dielectric between said gate and said charge storage layer.
Claim 10
Dependent Claim
25 words
The device according to claim 8 wherein said charge storage layer comprises silicon nitride and said top blocking dielectric comprises a layer of silicon dioxide.
Claim 11
Dependent Claim
18 words
The device according to claim 8 wherein said charge storage layer comprises a floating gate of conductive material.
Claim 12
Dependent Claim
25 words
The device according to claim 8 wherein said top blocking dielectric is a three layer composite structure of silicon dioxide, silicon nitride, and silicon dioxide.
Claim 13
Dependent Claim
20 words
The device according to claim 1 wherein said memory transistor is a SONOS tunneling metal insulator semiconductor field effect transistor.
Claim 14
Dependent Claim
14 words
The device according to claim 1 wherein said charge storage layer comprises silicon oxynitride.
Claim 15
Dependent Claim
18 words
The device according to claim 1 wherein said charge storage layer comprises a floating gate of conductive material.
Claim 16
Dependent Claim
25 words
The device according to claim 1 wherein said substrate has a first conductivity type and said source and drain regions have a second conductivity type.
Claim 17
Independent Claim
67 words
A method for preventing over erasure in a non-volatile memory cell, comprising: injecting a first current into the memory cell to erase the memory cell during an erase operation; injecting a second current into the memory cell, wherein said second current is injected during at least a period of time when said first current is injected, to prevent over erasure of the cell during the erase operation.
Claim 18
Independent Claim
67 words
A method for preventing over erasure in a non-volatile memory cell, comprising: injecting a first current into the memory cell to erase the memory cell during an erase operation; injecting a second current into the memory cell, wherein said second current is injected during at least a period of time when said first current is injected, to prevent over erasure of the cell during the erase operation.
Claim 19
Dependent Claim
17 words
The method of claim 16 further comprising adjusting said first and second currents to offset one another.
Claim 20
Dependent Claim
18 words
The method of claim 16 wherein said first and second currents are injected from respective separate injection nodes.
Claim 21
Dependent Claim
23 words
The method of claim 16 wherein said first and second currents are respectively dominant at different periods of time during the write operation.
Claim 22
Dependent Claim
13 words
The devices of claim 1 wherein said write operation comprises an erase operation.
Claim 23
Dependent Claim
13 words
The device of claim 1 wherein said write operation comprises a program operation.
Claim 24
Dependent Claim
15 words
The device of claim 1 wherein said predetermined value is an erased state threshold voltage.
Claim 25
Dependent Claim
15 words
The device of claim 1 wherein said predetermined value is a programmed state threshold voltage.
Claim 26
Independent Claim
123 words
A method for preventing over-writing a non-volatile memory cell during a write operation, wherein said write operation purposely changes the threshold voltage of a non-volatile transistor within said non-volatile memory cell, and wherein said over-writing inadvertently results when said threshold voltage changes to a value beyond a predetermined level, comprising: injecting a first current into said non-volatile memory cell to purposely change said threshold voltage during a write operation; injecting a second current into said non-volatile memory cell to prevent over-writing said non-volatile memory cell; accumulating charge from said first and second currents within said non-volatile memory cell; and utilizing said accumulating charge to create an electric field that constrains changes in said first and second currents when they achieve respective predetermined levels.
Claim 27
Independent Claim
123 words
A method for preventing over-writing a non-volatile memory cell during a write operation, wherein said write operation purposely changes the threshold voltage of a non-volatile transistor within said non-volatile memory cell, and wherein said over-writing inadvertently results when said threshold voltage changes to a value beyond a predetermined level, comprising: injecting a first current into said non-volatile memory cell to purposely change said threshold voltage during a write operation; injecting a second current into said non-volatile memory cell to prevent over-writing said non-volatile memory cell; accumulating charge from said first and second currents within said non-volatile memory cell; and utilizing said accumulating charge to create an electric field that constrains changes in said first and second currents when they achieve respective predetermined levels.
Claim 28
Dependent Claim
14 words
The method according to claim 24 wherein said write operation comprises an erase operation.
Claim 29
Dependent Claim
14 words
The method according to claim 24 wherein said write operation comprises a program operation.
Claim 30
Dependent Claim
17 words
The method according to claim 24 wherein said non-volatile transistor comprises a floating-gate non-volatile field effect transistor.
Claim 31
Dependent Claim
18 words
The method according to claim 24 wherein said non-volatile memory transistor comprises a SONOS non-volatile field effect transistor.
Claim 32
Dependent Claim
19 words
The method according to claim 24 wherein said first and second currents are injected from respective separate injection nodes.
Claim 33
Dependent Claim
24 words
The method according to claim 24 wherein said first and second currents are respectively dominant at different periods of time during the write operation.
Claim 34
Dependent Claim
25 words
The method according to claim 24 wherein said respective predetermined levels for said first and second currents constitute values that are substantially equal in magnitude.
Claim 35
Dependent Claim
20 words
The method according to claim 24 wherein said first current is injected through the channel of said non-volatile memory transistor.
Claim 36
Dependent Claim
20 words
The method according to claim 24 wherein said second current is injected through the gate of said non-volatile memory transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |