US5774397A
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Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state
Assignee: Toshiba Corp
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Filing: 1996-09-10
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Granted: 1998-06-30
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Expires: 2016-09-10
Abstract
Abstract A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.
Inventors
- 👤 Tetsuo Endoh
- 👤 Yoshiyuki Tanaka
- 👤 Seiichi Aritome
- 👤 Riichiro Shirota
- 👤 Susumu Shuto
- 👤 Tomoharu Tanaka
- 👤 Gertjan Hemink
- 👤 Toru Tanzawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:52
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/06; G11C16/08; G11C16/10; G11C16/12; G11C16/14; G11C16/34; G11C16/3404; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C16/3468; G11C16/3477; G11C16/3486; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621
Claims Analysis
Total Claims: 59
Claim 1
Independent Claim
113 words
A method of programming a non-volatile memory cell to a predetermined state, comprising: applying a programming pulse to said memory cell so as to program said memory cell to said predetermined state, said programming pulse having a programming voltage gradually raised up and being divided into plurality of sub-pulses; determining whether said memory cell has been successfully programmed to said predetermined stated; and terminating application of said programming pulse to said memory cell if said memory cell has been successfully programmed to said predetermined state; wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 2
Independent Claim
113 words
A method of programming a non-volatile memory cell to a predetermined state, comprising: applying a programming pulse to said memory cell so as to program said memory cell to said predetermined state, said programming pulse having a programming voltage gradually raised up and being divided into plurality of sub-pulses; determining whether said memory cell has been successfully programmed to said predetermined stated; and terminating application of said programming pulse to said memory cell if said memory cell has been successfully programmed to said predetermined state; wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein said programming pulse has a staircase shape.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein said programming pulse has a trapezoidal shape.
Claim 5
Dependent Claim
33 words
The method of claim 1 or 3, wherein whether said memory cell has been successfully programmed is determined during a time when said plurality of sub-pulses are not applied to said memory cell.
Claim 6
Dependent Claim
29 words
The method of claim 1, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cell to occur in a saturated region.
Claim 7
Dependent Claim
42 words
The method of claim 1, wherein said memory cell comprises a field effect transistor including a charge storage portion, said memory cell being coupled to a bitline at a drain electrode and being coupled to a word line at a gate electrode.
Claim 8
Dependent Claim
27 words
The method of claim 6, wherein said programming voltage is defined by a bitline voltage of said bitline and a word line voltage of said word line.
Claim 9
Dependent Claim
22 words
The method of claim 7, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 10
Dependent Claim
16 words
The method of claim 8, wherein said word line voltage is limited by a predetermined voltage.
Claim 11
Dependent Claim
42 words
The method of claim 8, comprising: arranging plural series connected memory cells in a NAND-cell unit, and gradually raising word line voltages of remaining memory cells in said NAND-cell unit from a word line voltage lower than a selected word line voltage.
Claim 12
Dependent Claim
21 words
The method of claim 7, wherein said word line voltage has a constant value and said bitline voltage is gradually decreased.
Claim 13
Dependent Claim
28 words
The method of claim 1, wherein said predetermined state is one of at least two states, and said memory cell stores one of said at least two states.
Claim 14
Dependent Claim
28 words
The method of claim 1, wherein said predetermined state is one of at least three states, and said memory cell stores one of said at least three states.
Claim 15
Dependent Claim
24 words
The method of claim 1, wherein said predetermined state in one of multi-level states, and said memory call stores one of said multi-level states.
Claim 16
Dependent Claim
26 words
The method of claim 14, wherein said programming voltage is determined by one of said multi-level states which is to be programmed into said memory cell.
Claim 17
Independent Claim
98 words
A method of programming a plurality of non-volatile memory cells to respective predetermined states, comprising: applying one or more programming pulses simultaneously to respective of said memory cells so as to program said memory cells to said respective predetermined states, said programming pulses having respective programming voltages gradually raised up; determining which of given memory cells to which a programming pulse has been applied have been successfully programmed to said respective predetermined states; and terminating application of a programming pulse to each of said given memory cells determined to have been successfully programmed to said predetermined state bit-by-bit.
Claim 18
Independent Claim
98 words
A method of programming a plurality of non-volatile memory cells to respective predetermined states, comprising: applying one or more programming pulses simultaneously to respective of said memory cells so as to program said memory cells to said respective predetermined states, said programming pulses having respective programming voltages gradually raised up; determining which of given memory cells to which a programming pulse has been applied have been successfully programmed to said respective predetermined states; and terminating application of a programming pulse to each of said given memory cells determined to have been successfully programmed to said predetermined state bit-by-bit.
Claim 19
Dependent Claim
13 words
The method of claim 16, wherein each programming pulse has a staircase shape.
Claim 20
Dependent Claim
13 words
The method of claim 16, wherein each programming pulse has a trapezoidal shape.
Claim 21
Dependent Claim
52 words
The method of claim 16, 17 or 18, wherein said programming pulses are divided into a plurality of sub-pulses and wherein whether each of said given memory cells has been successfully programmed is determined during a time when said plurality of sub-pulses are not applied to each of said given memory cells.
Claim 22
Dependent Claim
31 words
The method of claim 19, wherein a first pulse of said sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 23
Dependent Claim
29 words
The method of claim 20, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cells to occur in a saturated region.
Claim 24
Dependent Claim
50 words
The method of claim 16, wherein one of said memory cells has a structure of a field effect transistor including a charge storage portion, and each of said memory cells is coupled to a bitline at a drain electrode and is coupled to a word line at a gate electrode.
Claim 25
Dependent Claim
30 words
The method of claim 22, wherein each of said programming voltages is defined by a bitline voltage of the respective bitline and a word line voltage of said word line.
Claim 26
Dependent Claim
22 words
The method of claim 23, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 27
Dependent Claim
16 words
The method of claim 24, wherein said word line voltage is limited by a predetermined voltage.
Claim 28
Dependent Claim
42 words
The method of claim 24, comprising: arranging plural series connected memory cells in a NAND-cell unit, and gradually raising word line voltages of remaining memory cells in said NAND-cell unit from a word line voltage lower than a selected word line voltage.
Claim 29
Dependent Claim
21 words
The method of claim 23, wherein said word line voltage has a constant value and said bitline voltage is gradually decreased.
Claim 30
Dependent Claim
32 words
The method of claim 16, wherein each of said predetermined states is one of at least two states, and each of said memory cell stores one of said at least two states.
Claim 31
Dependent Claim
32 words
The method of claim 16, wherein each of said predetermined state is one of at least three states, and each of said memory cell stores one of said at least three states.
Claim 32
Dependent Claim
27 words
The method of claim 16, wherein each said predetermined state is one of multi-level states, and each of said memory cell stores one of said multi-level states.
Claim 33
Dependent Claim
25 words
The method of claim 30, wherein each programming voltage is determined by the predetermined state which is to be programmed into the corresponding memory cell.
Claim 34
Independent Claim
107 words
A method of erasing a non-volatile memory cell, comprising: applying one or more erasing pulses to said memory cell so as to erase said memory cell, each erasing pulse having an erasing voltage gradually raised up, and being divided into plurality of sub-pulses; determining whether said memory cell has been successfully erased; and terminating application of said erasing pulse to said memory cell when it is determined that said memory cell has been successfully erased to a predetermined state; wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 35
Independent Claim
107 words
A method of erasing a non-volatile memory cell, comprising: applying one or more erasing pulses to said memory cell so as to erase said memory cell, each erasing pulse having an erasing voltage gradually raised up, and being divided into plurality of sub-pulses; determining whether said memory cell has been successfully erased; and terminating application of said erasing pulse to said memory cell when it is determined that said memory cell has been successfully erased to a predetermined state; wherein a first pulse of said plurality of sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 36
Dependent Claim
13 words
The method of claim 32, wherein each erasing pulse has a staircase shape.
Claim 37
Dependent Claim
13 words
The method of claim 32, wherein each erasing pulse has a trapezoidal shape.
Claim 38
Independent Claim
34 words
The method of claims 32, 33 or 34, wherein whether said memory cell has been successfully erased is determined during a time when said plurality of sub-pulses are not applied to said memory cell.
Claim 39
Dependent Claim
29 words
The method of claim 32, wherein said first pulse duration of said first pulse is sufficient to cause erasing of said memory cell to occur in a saturated state.
Claim 40
Independent Claim
82 words
A method of erasing a plurality of non-volatile memory cells, comprising: applying erasing pulses simultaneously to respective of said memory cells so as to erase said memory cells, said erasing pulses each having an erasing voltage gradually raised up; determining which of given memory cells to which an erasing pulse was applied have been successfully erased; and terminating application of erasing pulses to each given memory cell when it is determined that the respective given memory cell has been successfully erased bit-by-bit.
Claim 41
Independent Claim
82 words
A method of erasing a plurality of non-volatile memory cells, comprising: applying erasing pulses simultaneously to respective of said memory cells so as to erase said memory cells, said erasing pulses each having an erasing voltage gradually raised up; determining which of given memory cells to which an erasing pulse was applied have been successfully erased; and terminating application of erasing pulses to each given memory cell when it is determined that the respective given memory cell has been successfully erased bit-by-bit.
Claim 42
Dependent Claim
13 words
The method of claim 37, wherein said erasing pulses has a staircase shape.
Claim 43
Dependent Claim
13 words
The method of claim 37, wherein said erasing pulses has a trapezoidal shape.
Claim 44
Dependent Claim
51 words
The method of claim 37, 38 or 39, wherein each of said erasing pulses is divided into a plurality of sub-pulses and wherein whether each of said memory cells is erased is determined during a time when said plurality of sub-pulses are not applied to each of said given memory cells.
Claim 45
Dependent Claim
31 words
The method of claim 40, wherein a first pulse of said sub-pulses has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 46
Dependent Claim
29 words
The method of claim 41, wherein said first pulse duration of said first pulse is sufficient to cause erasing of said memory cell to occur in a saturated region.
Claim 47
Dependent Claim
147 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bitlines; a plurality of word lines insulatively intersecting said bitlines; a memory cell array comprising a plurality of memory cells coupled to said bitlines and said word lines, each memory cell including a transistor with a charge storage portion; and a plurality of programming circuits coupled to said memory cell array, for storing control data which define whether or not programming pulses are to be applied to respective of said memory cells, said programming pulses having respective programming voltages gradually raised up, for applying said programming pulses to respective of said memory cells according to the control data stored by said programming circuits, and for selectively modifying said stored control data in order to apply said programming pulses only to memory cells in which it has been determined that data has not been successfully programmed.
Claim 48
Dependent Claim
147 words
A non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of bitlines; a plurality of word lines insulatively intersecting said bitlines; a memory cell array comprising a plurality of memory cells coupled to said bitlines and said word lines, each memory cell including a transistor with a charge storage portion; and a plurality of programming circuits coupled to said memory cell array, for storing control data which define whether or not programming pulses are to be applied to respective of said memory cells, said programming pulses having respective programming voltages gradually raised up, for applying said programming pulses to respective of said memory cells according to the control data stored by said programming circuits, and for selectively modifying said stored control data in order to apply said programming pulses only to memory cells in which it has been determined that data has not been successfully programmed.
Claim 49
Dependent Claim
13 words
The device of claim 43, wherein said programming pulses have a staircase shape.
Claim 50
Dependent Claim
13 words
The device of claim 43, wherein said programming pulses have a trapezoidal shape.
Claim 51
Dependent Claim
67 words
The device of claim 43, 44 or 45, wherein each of said programming pulses is divided into a plurality of sub-pulses and wherein said actual programmed states of said memory cells are determined when said sub-pulses are not applied to said respective memory cells, and said stored control data are modified during a time when said sub-pulses are not applied to said respective of said memory cells.
Claim 52
Dependent Claim
31 words
The device of claim 46, wherein a first pulse of said sub-pulse has a first pulse duration and pulse durations of remaining subsequent sub-pulses are shorter than said first pulse duration.
Claim 53
Dependent Claim
29 words
The device of claim 47, wherein said first pulse duration of said first pulse is sufficient to cause programming of said memory cell to occur in a saturated state.
Claim 54
Dependent Claim
37 words
The device of claim 43, wherein said programming voltages are simultaneously applied to said respective of said memory cells which are connected to respective one of said bitlines and commonly connected to one of said word lines.
Claim 55
Dependent Claim
30 words
The device of claim 49, wherein said programming voltages are defined by a bitline voltage of said respective one of bitlines and a word line voltage of said word line.
Claim 56
Dependent Claim
22 words
The device of claim 50, wherein said word line voltage is gradually raised up and said bitline voltage has a constant value.
Claim 57
Dependent Claim
17 words
The device or claim 51, wherein said word line voltage is limited by a predetermined maximum voltage.
Claim 58
Dependent Claim
62 words
The device of claim 51, comprising a NAND-cell unit including a plurality of memory cells connected in series, wherein a selected memory cell to be programmed is included in said NAND-cell unit, and word line voltages of remaining unselected memory cells in said NAND-cell unit are lower than the word line voltage of the related memory cell and are gradually raised up.
Claim 59
Dependent Claim
21 words
The device of claim 50, wherein said word line voltage has a constant value and said bitline voltage is gradually decreased.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |