US5774011A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Antifuse circuit using standard MOSFET devices
Assignee: International Business Machines Corp
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Filing: 1997-05-28
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Granted: 1998-06-30
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Expires: 2017-05-28
Abstract
Abstract A programmable device is formed from a field-effect transistor. Specifically, the present invention generally related to integrated circuit (IC) structures and more particularly, to an improved antifuse structure for use in programming redundant and customizable IC chips. The anti-fuse is NFET made of MOS material and formed at a face of a semiconductor layer having an n-type doped source, and drain region, and a p-type doped channel region separating the source and drain regions. The device is programmed by applying a high voltage to the NFET drain to form a hot spot located along the channel width of the drain and thereby forming a bridge, which now has less resistance than the surrounding channel material, to the NFET source.
Inventors
- 👤 Wai-Ming William Au
- 👤 Edward Joseph Nowak
- 👤 Ming Ho Tong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:05
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
105 words
An integrated circuit having an antifuse circuit for enabling a discretionary circuit, comprising: a) a first node having a programmable high voltage applied thereto; b) a PFET having: a gate, a source coupled to the first node, and a drain coupled to a second node and the discretionary circuit; c) a programmable circuit, coupled to the gate of the PFET, for pulling the PFET gate voltage high and low; and d) an NFET having a drain electrode coupled to the second node, the NFET gate having a channel region with a predetermined width and length that is shorted upon application of the programmable high voltage.
Claim 2
Dependent Claim
105 words
An integrated circuit having an antifuse circuit for enabling a discretionary circuit, comprising: a) a first node having a programmable high voltage applied thereto; b) a PFET having: a gate, a source coupled to the first node, and a drain coupled to a second node and the discretionary circuit; c) a programmable circuit, coupled to the gate of the PFET, for pulling the PFET gate voltage high and low; and d) an NFET having a drain electrode coupled to the second node, the NFET gate having a channel region with a predetermined width and length that is shorted upon application of the programmable high voltage.
Claim 3
Dependent Claim
28 words
The integrated circuit of claim 1 further comprising: an integrated circuit input pad, coupled to the first node, for applying the programmable high voltage to the first node.
Claim 4
Dependent Claim
25 words
The integrated circuit of claim 1 wherein the NFET is shorted by the programmable high voltage creating a hot spot in the NFET channel region.
Claim 5
Dependent Claim
17 words
The integrated circuit of claim 1 wherein the source of the NFET is coupled to the gate.
Claim 6
Dependent Claim
19 words
The integrated circuit of claim 1 wherein the gate of the NFET is coupled through a diode to ground.
Claim 7
Dependent Claim
18 words
The integrated circuit of claim 1 wherein the gate of the NFET is coupled to a floating node.
Claim 8
Dependent Claim
19 words
The integrated circuit of claim 1 wherein the gate of the NFET is coupled to a second control circuit.
Claim 9
Dependent Claim
16 words
The integrated circuit of claim 1 wherein the gate of the NFET is coupled to ground.
Claim 10
Dependent Claim
16 words
The integrated circuit of claim 3 wherein the high voltage is between 6 to 9 volts.
Claim 11
Dependent Claim
14 words
The integrated circuit of claim 3 wherein the high voltage is about 6.5 volts.
Claim 12
Dependent Claim
22 words
The integrated circuit of claim 10 wherein the NFET channel width is about 10 μm and channel length is about 0.5 μm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |