Low power, high performance junction transistor

Claim 2

An improved junction transistor formed on a semiconductor substrate, the junction transistor switching when a threshold gate voltage is applied, the transistor comprising: a well region having an average dopant concentration of a first conductivity type extending from a top surface of the semiconductor substrate downward into the substrate; a source region of a second conductivity type positioned within said well region; a drain region of the second conductivity type positioned within said well region; a channel region within said well region and separating the source and drain regions, wherein said channel region has a width of about 2 microns or less and a dopant concentration in the channel region is between about 1×10 14 and 1×10 16 atoms/cm 3 ; a gate positioned over the top surface of the substrate and over the channel region, said gate having an electrically tunable threshold voltage and having a threshold voltage magnitude of at most about 150 mV at room temperature; and a buried region of the first conductivity type within the well region and disposed beneath of the channel region and spanning the length of the channel region, said buried region having a dopant concentration of the first conductivity type that is between about 10 and 100 times greater than the average dopant concentration in the well region, wherein the buried region dopant concentration is between about 1×10 17 and 1×10 18 atoms/cm 3 ; and a contact connected to the source region and an ohmic contact connected to the well region such that the potential difference between the source and well regions can be adjusted to tune the gate threshold voltage by back biasing.

Claim 3

The improved junction transistor of claim 1 wherein the buried region is a buried electrode.

Claim 4

The improved junction transistor of claim 1 wherein the buried region forms part of a retrograde well having a graded dopant concentration of the first conductivity type such that the dopant concentration is greater near a bottom of the well.

Claim 5

The improved junction transistor of claim 1 wherein the gate is a floating gate having a tunable threshold voltage.

Claim 6

The improved junction transistor of claim 1 wherein a gate threshold voltage has a magnitude of at most about 120 mV.

Claim 7

The MOS transistor of claim 1 wherein the dopant concentration of the second conductivity type in the source and drain regions is 5×10 19 and 2×10 20 atoms/cm 3 adjacent the channel region.

Claim 8

The MOS transistor of claim 1 wherein the buried region is located such that it does contact either the source or the drain region.

Claim 9

A MOS transistor formed on semiconductor substrate, the MOS transistor switching when a threshold gate voltage is applied, the transistor comprising: a well region having an average dopant concentration of a first conductivity type extending from a top surface of the semiconductor substrate downward into the substrate; a source region of a second conductivity type positioned within said well region; a drain region of the second conductivity type positioned within said well region; a channel region within said well region and separating the source and drain regions, wherein said channel region has a width of about 2 microns or less and a dopant concentration in the channel region is between about 1×10 14 and 1×10 16 atoms/cm 3 ; a gate positioned over the channel region, said gate having an electrically tunable threshold voltage at which a device current is at most about 2 decades greater than at a point of zero gate voltage on a subthreshold region of a current versus gate voltage curve for said transistor such that the threshold voltage has a magnitude of at most about 150 mV at room temperature; and a buried electrode of the first conductivity type within the well region and disposed outside of and beneath the channel region, said buried electrode having a dopant concentration of the first conductivity type that is between about 10 and 100 times greater than the average dopant concentration in the well region, wherein the buried electrode dopant concentration is between about 1×10 17 and 1×10 18 atoms/cm 3 ; and a contact connected to the source region and an ohmic contact connected to the well region such that the potential difference between the source and well regions can be adjusted to tune the gate threshold voltage by back biasing.

Claim 10

A MOS transistor formed on semiconductor substrate, the MOS transistor switching when a threshold gate voltage is applied, the transistor comprising: a well region having an average dopant concentration of a first conductivity type extending from a top surface of the semiconductor substrate downward into the substrate; a source region of a second conductivity type positioned within said well region; a drain region of the second conductivity type positioned within said well region; a channel region within said well region and separating the source and drain regions, wherein said channel region has a width of about 2 microns or less and a dopant concentration in the channel region is between about 1×10 14 and 1×10 16 atoms/cm 3 ; a gate positioned over the channel region, said gate having an electrically tunable threshold voltage at which a device current is at most about 2 decades greater than at a point of zero gate voltage on a subthreshold region of a current versus gate voltage curve for said transistor such that the threshold voltage has a magnitude of at most about 150 mV at room temperature; and a buried electrode of the first conductivity type within the well region and disposed outside of and beneath the channel region, said buried electrode having a dopant concentration of the first conductivity type that is between about 10 and 100 times greater than the average dopant concentration in the well region, wherein the buried electrode dopant concentration is between about 1×10 17 and 1×10 18 atoms/cm 3 ; and a contact connected to the source region and an ohmic contact connected to the well region such that the potential difference between the source and well regions can be adjusted to tune the gate threshold voltage by back biasing.

Claim 11

The MOS transistor of claim 8 wherein the threshold voltage is between about +/-120 millivolts.

Claim 12

The MOS transistor of claim 8 wherein the buried electrode has a peak dopant concentration of greater than about 1×10 17 atoms/cm 3 .

Claim 13

The MOS transistor of claim 8 wherein the dopant concentration of the second conductivity type in the source and drain regions is 5×10 19 and 2×10 20 atoms/cm 3 adjacent the channel region.

Claim 14

The MOS transistor of claim 8 wherein the buried region is located such that it does not extend under either the entire source or the entire drain region.