Method of fabricating a linearly continuous integrated circuit gate array

Claim 1

An integrated circuit, comprising: a substrate of semiconductor material having an upper surface area; at least one pair of spaced apart elongated vertically extending columnar gate array fields defined on said upper surface area extending between two opposed boundary edges of said substrate; said gate array fields for the formation of individual logic gates therein; at least one pair of spaced apart elongated vertically extending columnar input/output device fields defined on said upper surface area sandwiched between said pair of gate array fields and extending between the opposed boundary edges; said input/output device fields for the formation of individual input/output circuits therein; an elongated vertically extending columnar connector pad field defined on said upper surface area sandwiched between said pair of input/output device fields and extending between the opposed boundary edges; said connector pad field having a plurality of electrical connector pads formed therein; and said logic gates, said input/output circuits and said electrical connector pads being arranged for electrical interconnection to accomplish a desired application functionality.

Claim 23

A method of making an integrated circuit having a substrate with at least one columnar gate array extending to opposing boundary edges thereof and being bound on one side only by parallel columnar arrays of input/output devices and connector pads, comprising: providing a substrate of semiconductor material having an upper surface area of a finite size; defining a plurality of pairs of spaced apart elongated vertically extending columnar gate array fields on said upper surface area extending between opposed boundary edges of said substrate; forming an array of logic gates in said gate array fields to facilitate the implementation of a desired logical functionality; defining a plurality of pairs of spaced apart elongated vertically extending columnar input/output device fields on said upper surface area extending between opposed boundary edges of said substrate; each individual pair of input/output device fields being sandwiched between associated adjacent individual pairs of said columnar gate array fields; forming individual input/output devices within said input/output fields to facilitate the implementation of a desired application functionality; forming a plurality of spaced apart elongated vertically extending columnar connector pad fields on said upper surface area extending between the opposed boundary edges of said substrate; each individual one of said connector pad fields being sandwiched between associated adjacent individual pairs of said input/output device fields and having formed therein a plurality of electrical connector pads to further facilitate the implementation of said desired application functionality; said logic gates, said input/output circuits and said electrical connector pads being arranged for electrical interconnection to facilitate implementation of said desired logical and application functionality purposes; wherein at least a pair of the columnar input/output devices include at least one branch input/output device field defined on said upper surface area extending horizontally outwardly into an adjacent gate array field to facilitate the electrical interconnection between individual input/output devices formed therein and individual logic gates formed in the adjacent gate array field; wherein one of said branch fields extends horizontally rightwardly into the adjacent gate array field toward, but short of, the next adjacent input/output device field; wherein another one of said branch fields extends horizontally leftwardly from the next adjacent input/output device field toward, but short of, the branch field extending horizontally rightward for defining a cutting street therebetween the branch fields; and wherein said substrate is separatable along said cutting street to form a logic gate array extending to opposing sides of a resulting die and being bound on one side only thereof by parallel arrays of input/output devices and connector pads.

Claim 24

A method of making an integrated circuit having a substrate with at least one columnar gate array extending to opposing boundary edges thereof and being bound on one side only by parallel columnar arrays of input/output devices and connector pads, comprising: providing a substrate of semiconductor material having an upper surface area of a finite size; defining a plurality of pairs of spaced apart elongated vertically extending columnar gate array fields on said upper surface area extending between opposed boundary edges of said substrate; forming an array of logic gates in said gate array fields to facilitate the implementation of a desired logical functionality; defining a plurality of pairs of spaced apart elongated vertically extending columnar input/output device fields on said upper surface area extending between opposed boundary edges of said substrate; each individual pair of input/output device fields being sandwiched between associated adjacent individual pairs of said columnar gate array fields; forming individual input/output devices within said input/output fields to facilitate the implementation of a desired application functionality; forming a plurality of spaced apart elongated vertically extending columnar connector pad fields on said upper surface area extending between the opposed boundary edges of said substrate; each individual one of said connector pad fields being sandwiched between associated adjacent individual pairs of said input/output device fields and having formed therein a plurality of electrical connector pads to further facilitate the implementation of said desired application functionality; said logic gates, said input/output circuits and said electrical connector pads being arranged for electrical interconnection to facilitate implementation of said desired logical and application functionality purposes; wherein at least a pair of the columnar input/output devices include at least one branch input/output device field defined on said upper surface area extending horizontally outwardly into an adjacent gate array field to facilitate the electrical interconnection between individual input/output devices formed therein and individual logic gates formed in the adjacent gate array field; wherein one of said branch fields extends horizontally rightwardly into the adjacent gate array field toward, but short of, the next adjacent input/output device field; wherein another one of said branch fields extends horizontally leftwardly from the next adjacent input/output device field toward, but short of, the branch field extending horizontally rightward for defining a cutting street therebetween the branch fields; and wherein said substrate is separatable along said cutting street to form a logic gate array extending to opposing sides of a resulting die and being bound on one side only thereof by parallel arrays of input/output devices and connector pads.