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US5773359A Expired / Lapsed US ⏱️ 0.0 years remaining

Interconnect system and method of fabrication

Assignee: NXP USA Inc
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Filing: 1995-12-26
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Granted: 1998-06-30
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Expires: 2015-12-26
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Abstract

Abstract An interconnect system (31) includes an interconnect bump (29) over an under bump metallurgy (25). The under bump metallurgy (25) includes a barrier layer (26) having a barrier material such as titanium, an adhesion layer (28) having an adhesion material such as copper, and a mixture layer (27) having both the barrier material and the adhesion material. The mixture layer (27) is located between the barrier layer (26) and the adhesion layer (28), and the adhesion layer (28) is located between the mixture layer (27) and the interconnect bump (29). The interconnect bump (29) contains solder and is used as an etch mask when patterning the under bump metallurgy (25).

Inventors

  • 👤 Douglas G. Mitchell
  • 👤 Francis J. Carney
  • 👤 Eric J. Woolsey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 15:18
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/012; H10W72/01231; H10W72/01251; H10W72/019; H10W72/20; H10W72/251; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/951; H10W72/952

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 83 words
A method of manufacturing an interconnect system, the method comprising the steps of: providing a substrate; disposing an electrically conductive layer over the substrate; disposing a first layer over the electrically conductive layer, the first layer comprising a barrier material; disposing a second layer over the first layer, the second layer comprising an adhesion material and the barrier material; and disposing a third layer over the second layer after the step of disposing the second layer, the third layer comprising the adhesion material.
Claim 2
Independent Claim 83 words
A method of manufacturing an interconnect system, the method comprising the steps of: providing a substrate; disposing an electrically conductive layer over the substrate; disposing a first layer over the electrically conductive layer, the first layer comprising a barrier material; disposing a second layer over the first layer, the second layer comprising an adhesion material and the barrier material; and disposing a third layer over the second layer after the step of disposing the second layer, the third layer comprising the adhesion material.
Claim 3
Dependent Claim 18 words
The method according to claim 1, further comprising the step of providing a passivation layer over the substrate.
Claim 4
Dependent Claim 55 words
The method according to claim 1, further comprising the steps of: providing an interconnect bump over the third layer, the interconnect bump coupled to the electrically conductive layer through the first, second, and third layers; etching the first, second, and third layers; and using the interconnect bump as an etch mask during the etching step.
Claim 5
Dependent Claim 19 words
The method according to claim 3, further comprising the step of providing tin and lead for the interconnect bump.
Claim 6
Dependent Claim 28 words
The method according to claim 1, further comprising the steps of: sputtering a first metal for the first layer; and sputtering a second metal for the third layer.
Claim 7
Dependent Claim 24 words
The method according to claim 5, further comprising the step of: providing titanium for the first metal; and providing copper for the second metal.
Claim 8
Independent Claim 119 words
A method of manufacturing a semiconductor component, the method comprising the steps of: providing a semiconductor substrate; fabricating an integrated circuit in the semiconductor substrate; forming a metal layer over the semiconductor substrate, the metal layer coupled to the integrated circuit; sputtering a barrier layer over the metal layer, the barrier layer having a barrier material; sputtering a mixture layer over the barrier layer, the mixture layer having the barrier material and an adhesion material; sputtering an adhesion layer over the mixture layer, the adhesion layer having the adhesion material; forming an interconnect bump over the adhesion layer; and using the interconnect bump as an etch mask while etching the adhesion layer, the mixture layer, and the barrier layer.
Claim 9
Independent Claim 119 words
A method of manufacturing a semiconductor component, the method comprising the steps of: providing a semiconductor substrate; fabricating an integrated circuit in the semiconductor substrate; forming a metal layer over the semiconductor substrate, the metal layer coupled to the integrated circuit; sputtering a barrier layer over the metal layer, the barrier layer having a barrier material; sputtering a mixture layer over the barrier layer, the mixture layer having the barrier material and an adhesion material; sputtering an adhesion layer over the mixture layer, the adhesion layer having the adhesion material; forming an interconnect bump over the adhesion layer; and using the interconnect bump as an etch mask while etching the adhesion layer, the mixture layer, and the barrier layer.
Claim 10
Dependent Claim 24 words
The method according to claim 7, further comprising the steps of: providing copper for the adhesion material; and providing titanium for the barrier layer.
Claim 11
Dependent Claim 25 words
The method according to claim 8, wherein the step of forming an interconnect bump includes plating solder over the adhesion layer and the metal layer.
Claim 12
Dependent Claim 43 words
The method according to claim 8, wherein the step of using the interconnect bump as an etch mask includes using a solution comprising hydrogen peroxide, ammonium hydroxide, and (ethylenedinitrilo) tetraacetic acid tetrasodium salt, dihydrate to etch the mixture layer and the barrier layer.
Claim 13
Dependent Claim 43 words
The method according to claim 8, wherein the step of using the interconnect bump as an etch mask includes using a solution comprising hydrogen peroxide, ammonium hydroxide, and (ethylenedinitrilo) tetraacetic acid disodium salt, dihydrate to etch the mixture layer and the barrier layer.

References Cited (Backward Citations)

JPS57154858A Cited
US5310699A Cited
JPS61251153A Cited
US5298459A Cited
JPH02253628A Cited
JPH04133330A Cited
JPH0513421A Cited
US5447599A Cited
US5470787A Cited
US5587336A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-29 2001-12-29 2002-06-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-29 2005-12-29 2006-06-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-29 2009-12-29 2010-06-30 $7700.00 Window Closed / Lapsed

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