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US5771346A
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Apparatus and method for detecting over-programming condition in multistate memory device
Assignee: Round Rock Research LLC
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Filing: 1996-10-24
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Granted: 1998-06-23
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Expires: 2016-10-24
Abstract
Abstract An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.
Inventors
- 👤 Robert D. Norman
- 👤 Christophe J. Chevallier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1072; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3413; G11C16/3418; G11C16/3436; G11C16/3454; G11C16/3463; G11C29/52; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C16/04; G11C29/04; G11C2029/0409; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5643
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
118 words
A multistate memory system comprising: an array of multistate memory cells; and a controller coupled to the array and configured to control data processing operations performed on the memory cells in the array, the controller comprising an over-programming condition detector configured to detect an over-programmed state of a memory cell in the array, wherein the over-programming condition detector comprises an error signal generator having a set of logic gates coupled to receive data programmed into the cell and data intended to be programmed into the cell, said set of logic gates being configured to assert an error signal when the data programmed into the cell is over-programmed relative to the data intended to be programmed into the cell.
Claim 2
Dependent Claim
118 words
A multistate memory system comprising: an array of multistate memory cells; and a controller coupled to the array and configured to control data processing operations performed on the memory cells in the array, the controller comprising an over-programming condition detector configured to detect an over-programmed state of a memory cell in the array, wherein the over-programming condition detector comprises an error signal generator having a set of logic gates coupled to receive data programmed into the cell and data intended to be programmed into the cell, said set of logic gates being configured to assert an error signal when the data programmed into the cell is over-programmed relative to the data intended to be programmed into the cell.
Claim 3
Dependent Claim
68 words
The multistate memory system of claim 1, wherein the controller further comprises circuitry coupled to the over-programming condition detector, said circuitry being configured to determine an address of the cell having said over-programmed state, said system also including: a processor coupled to the controller and configured to receive store the address of the cell having said over-programmed state and correct data for the cell having said over-programmed state.
Claim 4
Dependent Claim
34 words
The multistate memory system of claim 2, wherein the processor is configured to cause storage of the address and the correct data at the end of a sector of data containing the over-programmed data.
Claim 5
Dependent Claim
42 words
The multistate memory system of claim 2, wherein the processor is configured to cause storage of the address and the correct data at a location indicated by a pointer contained at the end of a sector of data containing the over-programmed data.
Claim 6
Dependent Claim
88 words
The multistate memory system of claim 1, wherein the over-programming condition detector is coupled to receive a byte-wide stream of data programmed into one or more cells of the array and a second byte-wide stream of data intended to be programmed into said one or more cells of the array, wherein the over-programming condition detector is configured to operate on the byte-wide stream and the second byte-wide stream on a byte-by-byte basis, and wherein the memory cell is one of said one or more cells of the array.
Claim 7
Dependent Claim
51 words
The multistate memory system of claim 1, also including a data bus of width N, said data bus being coupled to transfer data from the array to the over-programming condition detector, wherein the over-programming condition detector operates in parallel on N bits of data received in parallel over the data bus.
Claim 8
Dependent Claim
107 words
A multistate memory system, comprising: an array of multistate memory cells; and a controller for controlling data processing operations performed on the memory cells in the array the, controller further comprising: an over-programming condition detector configured to detect an over-programmed state of a memory cell in the array, wherein the over-programming condition detector comprises an error signal generator comprising a look up table coupled to receive data programmed into the cell and data intended to be programmed into the cell and configured to assert an error signal when the data programmed into the cell is over-programmed relative to the data intended to be programmed into the cell.
Claim 9
Dependent Claim
107 words
A multistate memory system, comprising: an array of multistate memory cells; and a controller for controlling data processing operations performed on the memory cells in the array the, controller further comprising: an over-programming condition detector configured to detect an over-programmed state of a memory cell in the array, wherein the over-programming condition detector comprises an error signal generator comprising a look up table coupled to receive data programmed into the cell and data intended to be programmed into the cell and configured to assert an error signal when the data programmed into the cell is over-programmed relative to the data intended to be programmed into the cell.
Claim 10
Independent Claim
149 words
A method for detecting an over-programmed condition of a multistate memory cell of a memory system and responding to detection of said over-programmed condition, comprising: reading data programmed into the memory cell of the memory system; reading data intended to be programmed into the memory cell; generating an over-program state error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell, by inputting the programmed data and the data intended to be programmed into the memory cell to a set of logic gates to cause said set of logic gates to assert the error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell; and storing an address of the memory cell and the data intended to be programmed into the memory cell when the over-program state error signal is asserted.
Claim 11
Independent Claim
149 words
A method for detecting an over-programmed condition of a multistate memory cell of a memory system and responding to detection of said over-programmed condition, comprising: reading data programmed into the memory cell of the memory system; reading data intended to be programmed into the memory cell; generating an over-program state error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell, by inputting the programmed data and the data intended to be programmed into the memory cell to a set of logic gates to cause said set of logic gates to assert the error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell; and storing an address of the memory cell and the data intended to be programmed into the memory cell when the over-program state error signal is asserted.
Claim 12
Dependent Claim
54 words
The method of claim 8, wherein the step of storing an address of the memory cell and the data intended to be programmed into the memory cell when the over-program state error signal is generated comprises: storing the address and the data at the end of a sector of data containing the over-programmed data.
Claim 13
Dependent Claim
62 words
The method of claim 8, wherein the step of storing an address of the memory cell and the data intended to be programmed into the memory cell when the over-program state error signal is generated comprises: storing the address and the data at a location indicated by a pointer contained at the end of a sector of data containing the over-programmed data.
Claim 14
Dependent Claim
114 words
The method of claim 8, wherein the data intended to be programmed into the memory cell is intended to be programmed as an element of a sector of data, and wherein the step of storing the address of the memory cell and the data intended to be programmed into the memory cell includes the steps of: appending said address of the memory cell and said data intended to be programmed into the memory cell at the end of the sector of data; and storing flag data indicating that said address of the memory cell and said data intended to be programmed into the memory cell have been appended at the end of the sector.
Claim 15
Dependent Claim
40 words
The method of claim 11, wherein the flag data has a selected one of a plurality of values, with each of said values corresponding to a data storage format for the data intended to be programmed into the memory cell.
Claim 16
Independent Claim
142 words
A method for detecting an over-programmed condition of a multistate memory cell of a memory system and responding to detection of said over-programmed condition, comprising the steps of: reading data programmed into the memory cell of the memory system; reading data intended to be programmed into the memory cell; asserting an over-program state error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell, by inputting the programmed data and the data intended to be programmed into the memory cell into a look up table which asserts the error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell; and storing an address of the memory cell and the data intended to be programmed into the memory cell when the error signal is asserted.
Claim 17
Independent Claim
142 words
A method for detecting an over-programmed condition of a multistate memory cell of a memory system and responding to detection of said over-programmed condition, comprising the steps of: reading data programmed into the memory cell of the memory system; reading data intended to be programmed into the memory cell; asserting an over-program state error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell, by inputting the programmed data and the data intended to be programmed into the memory cell into a look up table which asserts the error signal when the programmed data is over-programmed relative to the data intended to be programmed into the memory cell; and storing an address of the memory cell and the data intended to be programmed into the memory cell when the error signal is asserted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |