Patent US5771191A successfully refreshed from Google Patents.
US5771191A
Expired / Lapsed
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Method and system for inspecting semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1997-04-23
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Granted: 1998-06-23
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Expires: 2017-04-23
Abstract
Abstract A method for inspecting a semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection. The semiconductor memory device includes a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit. The method includes the steps of: deactivating the control circuit; connecting the inspection microcomputer and the memory to the control bus; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
Inventors
- 👤 Kazuki Matsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:32
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
107 words
A method for inspecting a semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof , a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the method including the steps of: deactivating the control circuit; connecting the inspection microcomputer and the memory to the control bus; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
Claim 2
Independent Claim
107 words
A method for inspecting a semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof , a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the method including the steps of: deactivating the control circuit; connecting the inspection microcomputer and the memory to the control bus; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
Claim 3
Dependent Claim
35 words
A method for inspecting a semiconductor memory device according to claim 1, further including the step of generating a control signal for controlling the inspection microcomputer based on the test program stored in the memory.
Claim 4
Independent Claim
138 words
A method for inspecting an one-chip semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device including, on a single chip, a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, a control bus for connecting the control circuit and the peripheral circuit, and an output terminal for sending a signal from the control bus outside the chip, the method comprising the steps of: inputting a control signal to the chip from the inspection microcomputer; deactivating the control circuit based on the control signal; connecting the inspection microcomputer to the output terminal; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
Claim 5
Independent Claim
138 words
A method for inspecting an one-chip semiconductor memory device by using an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device including, on a single chip, a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, a control bus for connecting the control circuit and the peripheral circuit, and an output terminal for sending a signal from the control bus outside the chip, the method comprising the steps of: inputting a control signal to the chip from the inspection microcomputer; deactivating the control circuit based on the control signal; connecting the inspection microcomputer to the output terminal; and inspecting the peripheral circuit and the non-volatile memory area by the inspection microcomputer.
Claim 6
Dependent Claim
30 words
A method for inspecting a semiconductor memory device according to claim 3, further including the step of generating the control signal based on the test program stored in the memory.
Claim 7
Independent Claim
122 words
A method for inspecting a semiconductor memory device by using an inspection apparatus and an inspection microcomputer provided with a memory storing a test program for the inspection, the semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the method including the steps of: deactivating the control circuit; selectively connecting one of the inspection apparatus and the inspection microcomputer to the control bus; and inspecting the peripheral circuit and the non-volatile memory area using the selected one of the inspection apparatus and the inspection microcomputer.
Claim 8
Independent Claim
122 words
A method for inspecting a semiconductor memory device by using an inspection apparatus and an inspection microcomputer provided with a memory storing a test program for the inspection, the semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the method including the steps of: deactivating the control circuit; selectively connecting one of the inspection apparatus and the inspection microcomputer to the control bus; and inspecting the peripheral circuit and the non-volatile memory area using the selected one of the inspection apparatus and the inspection microcomputer.
Claim 9
Dependent Claim
24 words
A method for inspecting a semiconductor memory device according to claim 5, wherein the step of selectively connecting is performed by a switching circuit.
Claim 10
Independent Claim
103 words
A system for inspecting a semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the system comprising: an inspection microcomputer for inspecting the peripheral circuit and the non-volatile memory area; and a memory for storing a test program for the inspection, wherein the inspection microcomputer outputs a control signal so as to deactivate the control circuit before performing the inspection by connecting to the control bus.
Claim 11
Independent Claim
103 words
A system for inspecting a semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the system comprising: an inspection microcomputer for inspecting the peripheral circuit and the non-volatile memory area; and a memory for storing a test program for the inspection, wherein the inspection microcomputer outputs a control signal so as to deactivate the control circuit before performing the inspection by connecting to the control bus.
Claim 12
Dependent Claim
29 words
A system for inspecting a semiconductor memory device according to claim 7, wherein the inspection microcomputer generates the control signal based on the test program stored in the memory.
Claim 13
Dependent Claim
21 words
A system for inspecting a semiconductor memory device according to claim 7, wherein the memory is built in the inspection microcomputer.
Claim 14
Dependent Claim
22 words
A system for inspecting a semiconductor memory device according to claim 7, wherein the memory is externally connected to the inspection microcomputer.
Claim 15
Independent Claim
151 words
A system for inspecting a semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the system including: an inspection apparatus and an inspection microcomputer for inspecting the peripheral circuit and the non-volatile memory area, one of the inspection apparatus and the inspection microcomputer outputting first and second control signals; and a switching circuit for selectively connecting one of the inspection apparatus and the inspection microcomputer to the control bus based on the first control signal, wherein the first control signal is generated based on the type of inspection to be performed, and the second control signal is input to the semiconductor memory device so as to deactivate the control circuit before performing the inspection.
Claim 16
Independent Claim
151 words
A system for inspecting a semiconductor memory device including a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the system including: an inspection apparatus and an inspection microcomputer for inspecting the peripheral circuit and the non-volatile memory area, one of the inspection apparatus and the inspection microcomputer outputting first and second control signals; and a switching circuit for selectively connecting one of the inspection apparatus and the inspection microcomputer to the control bus based on the first control signal, wherein the first control signal is generated based on the type of inspection to be performed, and the second control signal is input to the semiconductor memory device so as to deactivate the control circuit before performing the inspection.
Claim 17
Dependent Claim
36 words
A system for inspecting a semiconductor memory device according to claim 11, wherein the inspection microcomputer is provided with a memory storing a test program for the inspection, the memory being built in the inspection microcomputer.
Claim 18
Dependent Claim
37 words
A system for inspecting a semiconductor memory device according to claim 11, wherein the inspection microcomputer is provided with a memory storing a test program for the inspection, the memory being externally connected to the inspection microcomputer.
Claim 19
Dependent Claim
125 words
A one-chip semiconductor memory device including, on a single chip, a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the semiconductor memory device being inspectable in an inspection system including an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device further including: an output terminal for sending a signal from the control bus outside the chip, connectable to the inspection microcomputer; and means for receiving a control signal output from the inspection microcomputer and for deactivating the control circuit based on the control signal.
Claim 20
Dependent Claim
125 words
A one-chip semiconductor memory device including, on a single chip, a non-volatile memory area, a peripheral circuit thereof, a control circuit for controlling writing and erasing of data to and from the non-volatile memory area via the peripheral circuit, and a control bus for connecting the control circuit and the peripheral circuit, the semiconductor memory device being inspectable in an inspection system including an inspection microcomputer and a memory for storing a test program for the inspection, the semiconductor memory device further including: an output terminal for sending a signal from the control bus outside the chip, connectable to the inspection microcomputer; and means for receiving a control signal output from the inspection microcomputer and for deactivating the control circuit based on the control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |