US5768626A — Method and apparatus for servicing a plurality of…

Claim 1

Independent Claim 181 words

A method for servicing a plurality of FIFO buffers, each FIFO buffer receiving data entries as input and having an output controlled by a control unit for writing the data entries stored within the FIFO buffers onto a data bus, the method comprising the steps of: generating a first trip point signal for each FIFO buffer having a depth value equal to or greater than a first trip point value but less than a second trip point value; generating a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value; issuing FIFO service requests from a logic unit to the control unit in accordance with a prioritization scheme for the generated trip point signals, said prioritization scheme selecting among the FIFO buffers for providing data entries to the bus; and servicing the plurality of FIFO buffers in accordance with the prioritization scheme including preempting the service of any FIFO buffer currently being serviced upon generation of a trip point signal having a higher priority according to the prioritization scheme.

Claim 2

Independent Claim 181 words

A method for servicing a plurality of FIFO buffers, each FIFO buffer receiving data entries as input and having an output controlled by a control unit for writing the data entries stored within the FIFO buffers onto a data bus, the method comprising the steps of: generating a first trip point signal for each FIFO buffer having a depth value equal to or greater than a first trip point value but less than a second trip point value; generating a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value; issuing FIFO service requests from a logic unit to the control unit in accordance with a prioritization scheme for the generated trip point signals, said prioritization scheme selecting among the FIFO buffers for providing data entries to the bus; and servicing the plurality of FIFO buffers in accordance with the prioritization scheme including preempting the service of any FIFO buffer currently being serviced upon generation of a trip point signal having a higher priority according to the prioritization scheme.

Claim 3

Dependent Claim 53 words

The method of claim 1, wherein when no second trip point signals have been generated, the step of servicing the plurality of FIFO buffers in accordance with the prioritization scheme comprises the step of servicing in order of trip point signal generation those FIFO buffers having an associated first trip point signal generated.

Claim 4

Dependent Claim 56 words

The method of claim 1, wherein when second trip point signals have been generated for each FIFO buffer, the step of servicing the plurality of FIFO buffers in accordance with the prioritization scheme comprises the step of servicing in order of trip point signal generation those FIFO buffers having an associated second trip point signal generated.

Claim 5

Dependent Claim 80 words

The method of claim 1, wherein when at least one FIFO buffer has an associated first trip point signal generated and at least one other FIFO buffer has an associated second trip point signal generated, the step of servicing the plurality of FIFO buffers in accordance with the prioritization scheme comprises the step of servicing those FIFO buffers having an associated second trip point signal generated before servicing of those FIFO buffers having an associated first trip point signal generated.

Claim 6

Dependent Claim 110 words

The method of claim 1, wherein when at least one FIFO buffer has an associated first trip point signal generated, at least one other FIFO buffer has an associated second trip point signal generated and a FIFO buffer having an associated first trip point signal generated is being currently serviced, the step of servicing the plurality of FIFO buffers in accordance with the prioritization scheme comprises the step of preempting servicing of the FIFO buffer currently being serviced upon receipt of a second trip point signal associated with another FIFO buffer, each FIFO buffer having an associated second trip point signal being serviced in order of trip point signal generation.

Claim 7

Dependent Claim 42 words

The method of claim 1, wherein the plurality of FIFO buffers comprises three FIFO buffers of a capture gate array coupled to a video processing device for storing respective Y, U and V bitmap data entries input to the capture gate array.

Claim 8

Dependent Claim 268 words

A memory access unit for use in prioritizing the servicing of FIFO buffers in a capture gate array, the CGA being coupled to a video processing device and comprising at least a FIFO Unit having a plurality of FIFO buffers for receiving as input to the CGA separated Y, U, and V bitmap data entries and a bus interface unit coupled to a video memory bus for outputting the data entries to the video processing device, the memory access unit comprising: a signal generation unit having as input from the FIFO Unit depth values for the FIFO buffers representing the number of data entries currently stored in respective FIFO buffers, the signal generation unit generating a first trip point signal for each FIFO buffer having a depth value equal to or greater than a first trip point value but less than a second trip point value and generating a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value; a logic unit coupled to the signal generation unit and comprising logic for prioritizing the generated trip point signals associated with the respective FIFO buffers, the logic unit further generating FIFO service requests in accordance with the prioritized trip point signals; and a control unit coupled between the logic unit and the bus interface unit, the control unit selecting among the FIFO buffers for providing data entries to the bus interface unit and the control unit preempting the service of any FIFO buffer currently being serviced upon generation of a trip point signal having a higher priority.

Claim 9

Dependent Claim 268 words

A memory access unit for use in prioritizing the servicing of FIFO buffers in a capture gate array, the CGA being coupled to a video processing device and comprising at least a FIFO Unit having a plurality of FIFO buffers for receiving as input to the CGA separated Y, U, and V bitmap data entries and a bus interface unit coupled to a video memory bus for outputting the data entries to the video processing device, the memory access unit comprising: a signal generation unit having as input from the FIFO Unit depth values for the FIFO buffers representing the number of data entries currently stored in respective FIFO buffers, the signal generation unit generating a first trip point signal for each FIFO buffer having a depth value equal to or greater than a first trip point value but less than a second trip point value and generating a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value; a logic unit coupled to the signal generation unit and comprising logic for prioritizing the generated trip point signals associated with the respective FIFO buffers, the logic unit further generating FIFO service requests in accordance with the prioritized trip point signals; and a control unit coupled between the logic unit and the bus interface unit, the control unit selecting among the FIFO buffers for providing data entries to the bus interface unit and the control unit preempting the service of any FIFO buffer currently being serviced upon generation of a trip point signal having a higher priority.

Claim 10

Dependent Claim 39 words

The memory access unit of claim 7, wherein when no second trip point signals have been generated, the control unit services in order of trip point signal generation those FIFO buffers having an associated first trip point signal generated.

Claim 11

Dependent Claim 42 words

The memory access unit of claim 7, wherein when second trip point signals have been generated for each FIFO buffer, the control unit services in order of trip point signal generation those FIFO buffers having an associated second trip point signal generated.

Claim 12

Dependent Claim 66 words

The memory access unit of claim 7, wherein when at least one FIFO buffer has an associated first trip point signal generated and at least one other FIFO buffer has an associated second trip point signal generated, the control unit services those FIFO buffers having an associated second trip point signal generated before servicing of those FIFO buffers having an associated first trip point signal generated.

Claim 13

Dependent Claim 98 words

The memory access unit of claim 7, wherein when at least one FIFO buffer has an associated first trip point signal generated, at least one other FIFO buffer has an associated second trip point signal generated and a FIFO buffer having an associated first trip point signal generated is being currently serviced, the control unit preempts servicing of the FIFO buffer currently being serviced upon receipt of a second trip point signal associated with another FIFO buffer, the control unit servicing in order of trip point signal generation each FIFO buffer having an associated second trip point signal.

Claim 14

Independent Claim 162 words

A method for servicing a plurality of FIFO buffers, each FIFO buffer receiving data entries as input and having an output controlled by a control unit for writing the data entries stored within the FIFO buffers onto a data bus, the method comprising the steps of: calculating the number of data entries currently stored in a reference FIFO buffer to obtain a depth value for the reference FIFO buffer; associating each FIFO buffer with a predetermined constant value representing a predetermined number of data entries within a reference FIFO buffer, the constants comprising sequentially larger values for succeeding larger values for succeeding FIFO buffers; comparing separately the depth value of the reference FIFO buffer with each constant value associated with each respective FIFO buffer; generating a trip signal for each FIFO buffer having an associated constant value equal to or less than the depth value of the reference FIFO buffer; and servicing the FIFO buffers sequentially in accordance with trip signal generation.

Claim 15

Independent Claim 162 words

A method for servicing a plurality of FIFO buffers, each FIFO buffer receiving data entries as input and having an output controlled by a control unit for writing the data entries stored within the FIFO buffers onto a data bus, the method comprising the steps of: calculating the number of data entries currently stored in a reference FIFO buffer to obtain a depth value for the reference FIFO buffer; associating each FIFO buffer with a predetermined constant value representing a predetermined number of data entries within a reference FIFO buffer, the constants comprising sequentially larger values for succeeding larger values for succeeding FIFO buffers; comparing separately the depth value of the reference FIFO buffer with each constant value associated with each respective FIFO buffer; generating a trip signal for each FIFO buffer having an associated constant value equal to or less than the depth value of the reference FIFO buffer; and servicing the FIFO buffers sequentially in accordance with trip signal generation.

Claim 16

Dependent Claim 205 words

The method of claim 12, wherein the steps of comparing separately the depth value of the reference FIFO buffer with each constant value associated with each respective FIFO buffer, generating a trip signal for each FIFO buffer having an associated constant value equal to or less than the depth value of the reference FIFO buffer and servicing the FIFO buffers sequentially in accordance with trip signal generation comprise the steps of: inputting the depth value of the reference FIFO buffer into a comparator associated with each FIFO buffer, the comparator further having as input the constant value associated with each FIFO buffer; outputting from each comparator a trip signal associated with the respective FIFO buffer when the constant value of the respective FIFO buffer is equal to or less than the depth value of the reference FIFO buffer; inputting to an AND gate provided for each FIFO buffer the trip point signal associated with the respective FIFO buffer, each AND gate further having as input an inverted output from each AND gate of a succeeding FIFO buffer; and transmitting the output of each AND gate to the control unit to initiate servicing of a FIFO buffer having an associated AND gate with an asserted output.

Claim 17

Dependent Claim 42 words

The method of claim 12, wherein the plurality of FIFO buffers comprises three FIFO buffers of a capture gate array coupled to a video processing device for storing respective Y, U and V bitmap data entries input to the capture gate array.

Claim 18

Dependent Claim 49 words

The method of claim 1, wherein the plurality of FIFO buffers includes a set of FIFO buffers, the set containing more than one FIFO buffer, such that all FIFO buffers in the set are in either a read state or a write state with respect to the data bus.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-06-15	2001-12-15	2002-06-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-06-15	2005-12-15	2006-06-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-06-15	2009-12-15	2010-06-16	$7700.00	Window Closed / Lapsed

Method and apparatus for servicing a plurality of FIFO's in a capture gate array

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