Interrupt controller optimized for power management in a computer system or subsystem

Claim 2

A computer system comprising: a plurality of peripheral devices capable of asserting interrupt request signals; an interrupt controller including a plurality of interrupt request lines for receiving said interrupt request signals, wherein said interrupt controller includes a control circuit capable of generating a microprocessor interrupt signal in response to the assertion of one of said interrupt request signals, and wherein said interrupt controller further includes an in-service register configured to store data indicative of which of said interrupt request signals is currently being serviced by a microprocessor; and a power management unit coupled to an output line of said in-service register, wherein said power management unit is configured to change a frequency of a clock signal a predetermined delay after said data stored in said in-service register indicates that none of said interrupt request signals are currently being serviced by said microprocessor, wherein a duration of said predetermined delay depends on which of said interrupt request signals was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller.

Claim 3

The computer system as recited in claim 1 wherein said interrupt controller further comprises: an interrupt request register coupled to said plurality of interrupt request lines for receiving and storing the identity of any said plurality of interrupt lines which is requesting an interrupt, wherein each of said plurality of interrupt request signals has a predetermined priority level programmed by the user.

Claim 4

The computer system as recited in claim 2 wherein said interrupt request register is further coupled to a priority resolver circuit for prioritizing said plurality of interrupt signals based on said predetermined priority levels.

Claim 5

The computer system as recited in claim 1 wherein said clock signal is provided to clock said microprocessor.

Claim 6

The computer system as recited in claim 1 wherein said clock signal is provided to clock a computer subsystem.

Claim 7

The computer system as recited in claim 1 wherein said power management unit changes said frequency of said clock signal substantially immediately after an interrupt request signal from a first peripheral device is serviced.

Claim 8

The computer system as recited in claim 1 wherein said power management unit changes said frequency of said clock signal a first predetermined delay after an interrupt request signal from a second peripheral device is serviced.

Claim 9

The computer system as recited in claim 7 wherein a keyboard is said second peripheral device.

Claim 10

The computer system as recited in claim 7 wherein said power management unit stops said clock signal.

Claim 11

The computer system as recited in claim 9 wherein said power management unit stops said clock signal only if no interrupt request signals are being serviced by said microprocessor.

Claim 12

A computer system comprising: a plurality of peripheral devices capable of asserting interrupt request signals; an interrupt controller including a plurality of interrupt request lines for receiving said interrupt request signals, wherein said interrupt controller includes a priority control circuit capable of generating a microprocessor interrupt signal in response to the assertion of one of said interrupt request signals, and wherein said interrupt controller further includes an in-service register configured to store data indicative of which of said interrupt request signals is currently being serviced by a microprocessor; and a power management unit coupled to an output line of said in-service register, wherein said power management unit is configured to remove power supplied to a computer subsystem a predetermined delay after said in-service register indicates that none of said interrupt request signals are currently being serviced by said microprocessor, wherein a duration of said predetermined delay depends on which of said interrupt request signals was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller.

Claim 13

A computer system comprising: a plurality of peripheral devices capable of asserting interrupt request signals; an interrupt controller including a plurality of interrupt request lines for receiving said interrupt request signals, wherein said interrupt controller includes a priority control circuit capable of generating a microprocessor interrupt signal in response to the assertion of one of said interrupt request signals, and wherein said interrupt controller further includes an in-service register configured to store data indicative of which of said interrupt request signals is currently being serviced by a microprocessor; and a power management unit coupled to an output line of said in-service register, wherein said power management unit is configured to remove power supplied to a computer subsystem a predetermined delay after said in-service register indicates that none of said interrupt request signals are currently being serviced by said microprocessor, wherein a duration of said predetermined delay depends on which of said interrupt request signals was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller.

Claim 14

The computer system as recited in claim 11 wherein said interrupt controller further comprises: an interrupt request register coupled to said plurality of interrupt request lines for receiving and storing the identity of any said plurality of interrupt lines which is requesting an interrupt, wherein each of said plurality of interrupt request signals has a predetermined priority level programmed by the user.

Claim 15

The computer system as recited in claim 12 wherein said interrupt request register is further coupled to a priority resolver circuit for prioritizing said plurality of interrupt signals.

Claim 16

The computer system as recited in claim 11 wherein said power management unit removes power to said computer subsystem substantially immediately after an interrupt request signal from a first peripheral device is serviced.

Claim 17

The computer system as recited in claim 11 wherein said power management unit removes power supplied to said computer subsystem a first predetermined delay after an interrupt request signal from a second peripheral device is serviced.

Claim 18

The computer system as recited in claim 15 wherein said power management unit causes power to be removed from said computer subsystem only if no interrupt requests are being serviced by said microprocessor.

Claim 19

An interrupt controller fabricated on an integrated circuit chip, comprising: an interrupt request register for receiving a plurality of interrupt request signals from a plurality of peripheral devices; a priority resolver circuit coupled to said interrupt request register for directing the servicing of a highest priority interrupt request signal; a control circuit for generating a microprocessor interrupt signal for a microprocessor to invoke a microprocessor interrupt service routine, wherein said generating a microprocessor interrupt signal occurs in response to said highest priority interrupt request signal, wherein said control circuit is configured to receive an acknowledge signal generated by said microprocessor; an in-service register coupled to said control circuit for storing data indicative of whether any of said interrupt request signals are currently being serviced by said microprocessor; and an output terminal coupled to an output line of said in-service register, wherein said output terminal is configured to be connected to devices that are external to said integrated circuit chip, and provides a signal indicative of which of said interrupt request signals is currently being serviced by said microprocessor.

Claim 20

An interrupt controller fabricated on an integrated circuit chip, comprising: an interrupt request register for receiving a plurality of interrupt request signals from a plurality of peripheral devices; a priority resolver circuit coupled to said interrupt request register for directing the servicing of a highest priority interrupt request signal; a control circuit for generating a microprocessor interrupt signal for a microprocessor to invoke a microprocessor interrupt service routine, wherein said generating a microprocessor interrupt signal occurs in response to said highest priority interrupt request signal, wherein said control circuit is configured to receive an acknowledge signal generated by said microprocessor; an in-service register coupled to said control circuit for storing data indicative of whether any of said interrupt request signals are currently being serviced by said microprocessor; and an output terminal coupled to an output line of said in-service register, wherein said output terminal is configured to be connected to devices that are external to said integrated circuit chip, and provides a signal indicative of which of said interrupt request signals is currently being serviced by said microprocessor.

Claim 21

The interrupt controller as recited in claim 17 wherein a second output terminal is coupled to a second output line of said in-service register, wherein said second output terminal is capable of being connected to devices that are external to said integrated circuit.

Claim 22

The interrupt controller as recited in claim 17 wherein said in-service register includes at least one latch, wherein said latch is set if one of said interrupt request signals is being serviced by a microprocessor and wherein said latch is cleared if said one of said interrupt request signals is not being serviced by said microprocessor.

Claim 23

A computer system comprising: a plurality of peripheral devices capable of asserting interrupt request signals; an interrupt controller including a plurality of interrupt request lines, wherein said plurality of interrupt request lines includes a first interrupt request line and a second interrupt request line, wherein said first interrupt request line is configured to receive a first interrupt request signal and said second interrupt request line is configured to receive a second interrupt request signal, wherein said interrupt controller includes a control circuit capable of generating a microprocessor interrupt signal in response to the assertion of said first interrupt request signal or said second interrupt request signal, and wherein said interrupt controller further includes an in-service register configured to store data indicative of which of said first interrupt request signal or said second interrupt request signal is currently being serviced by a microprocessor; and a power management unit coupled to an output line of said in-service register, wherein said power management unit is configured to change a frequency of a clock signal a predetermined delay after said data stored in said in-service register indicates that none of said interrupt request signals are currently being serviced by said microprocessor, wherein a duration of said predetermined delay is a first duration if said first interrupt request signal was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller and a second duration if said second interrupt request signal was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller, wherein said second duration is different from said first duration.

Claim 24

A computer system comprising: a plurality of peripheral devices capable of asserting interrupt request signals; an interrupt controller including a plurality of interrupt request lines, wherein said plurality of interrupt request lines includes a first interrupt request line and a second interrupt request line, wherein said first interrupt request line is configured to receive a first interrupt request signal and said second interrupt request line is configured to receive a second interrupt request signal, wherein said interrupt controller includes a control circuit capable of generating a microprocessor interrupt signal in response to the assertion of said first interrupt request signal or said second interrupt request signal, and wherein said interrupt controller further includes an in-service register configured to store data indicative of which of said first interrupt request signal or said second interrupt request signal is currently being serviced by a microprocessor; and a power management unit coupled to an output line of said in-service register, wherein said power management unit is configured to change a frequency of a clock signal a predetermined delay after said data stored in said in-service register indicates that none of said interrupt request signals are currently being serviced by said microprocessor, wherein a duration of said predetermined delay is a first duration if said first interrupt request signal was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller and a second duration if said second interrupt request signal was last serviced by said microprocessor as indicated by said data stored in said in-service register of said interrupt controller, wherein said second duration is different from said first duration.