Patent US5764930A successfully refreshed from Google Patents.
US5764930A
Expired / Lapsed
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Method and apparatus for providing reset transparency on a reconfigurable bus
Assignee: Apple Inc
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Filing: 1996-04-01
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Granted: 1998-06-09
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Expires: 2016-04-01
Abstract
Abstract A computer system includes a plurality of nodes, each having an associated unique identification and bus address, interconnected by point-to-point links. Device data records are maintained in a memory of the computer system wherein node unique identifications, which are bus reset invariant, are associated with corresponding node bus addresses, which are subject to change with bus resets. A driver associated with a source node initiates a bus transaction and specifies a reference identification for the destination node. The reference identification of the destination node is used to access the device data records to obtain the corresponding destination node bus address. When a bus transaction cannot be completed because a bus reset occurs, the device data records are updated to associate the new bus addresses of the nodes with the corresponding node unique identifications. The new destination node bus address is used to complete the bus transaction that was interrupted by the bus reset.
Inventors
- 👤 Erik P. Staats
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:43
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40078; G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; H04L12/40071
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
62 words
A computer implemented method comprising: initiating a bus transaction between a source node and a destination node, said bus transaction comprising a bus-reset invariant reference identification associated with said destination node; associating said bus-reset invariant reference identification with a corresponding non-reset invariant logical bus address associated with said destination node; and completing said bus transaction utilizing said non-reset invariant logical bus address.
Claim 2
Dependent Claim
62 words
A computer implemented method comprising: initiating a bus transaction between a source node and a destination node, said bus transaction comprising a bus-reset invariant reference identification associated with said destination node; associating said bus-reset invariant reference identification with a corresponding non-reset invariant logical bus address associated with said destination node; and completing said bus transaction utilizing said non-reset invariant logical bus address.
Claim 3
Dependent Claim
61 words
The method of claim 1 wherein said step of associating comprises: using said bus-reset invariant reference identification to access a data structure stored in a computer-readable memory, said data structure comprising said non-reset invariant logical bus address and a bus-reset invariant unique identification associated with said destination node; and retrieving from said data structure said corresponding non-reset invariant logical bus address.
Claim 4
Dependent Claim
90 words
The method of claim 2 further comprising: receiving a bus indication prior to said step of completing said bus transaction; replacing said non-reset invariant logical bus address with an updated non-reset invariant logical bus address associated with said destination node in said data structure; using said bus-reset invariant reference identification to access said data structure; retrieving from said data structure said updated non-reset invariant logical bus address; and using said updated non-reset invariant logical bus address in place of said non-reset invariant logical bus address to complete said bus transaction.
Claim 5
Dependent Claim
23 words
The method of claim 3 further comprising: disabling a local host associated with said source node in response to said bus reset indication.
Claim 6
Dependent Claim
82 words
A computer-readable medium comprising: computer readable instructions which, when executed by a processor coupled to a bus, cause said processor to perform the computer implemented steps of: (a) initiating a bus transaction comprising a bus-reset invariant reference identification for a destination node coupled to said bus; (b) associating said bus-reset invariant reference identification for said destination node with a corresponding non-reset invariant logical bus address for said destination node; and (c) completing said bus transaction utilizing said non-reset invariant logical bus address.
Claim 7
Dependent Claim
82 words
A computer-readable medium comprising: computer readable instructions which, when executed by a processor coupled to a bus, cause said processor to perform the computer implemented steps of: (a) initiating a bus transaction comprising a bus-reset invariant reference identification for a destination node coupled to said bus; (b) associating said bus-reset invariant reference identification for said destination node with a corresponding non-reset invariant logical bus address for said destination node; and (c) completing said bus transaction utilizing said non-reset invariant logical bus address.
Claim 8
Dependent Claim
82 words
A computer readable medium as in claim 5 further comprising additional computer readable instructions which, when executed by said processor during said step of associating, cause said processor to perform the computer implemented steps of: using said bus-reset invariant reference identification to access a data structure stored in a memory, said data structure comprising a reset invariant unique identification for said destination node and said non-reset invariant logical bus address; and retrieving from said data structure said non-reset invariant logical bus address.
Claim 9
Dependent Claim
82 words
A computer-readable medium as in claim 6 further comprising computer readable instructions which, when executed by said processor in response to a bus reset indication, cause said processor to perform the computer implemented steps of: updating said data structure such that said reset invariant unique identification is associated with an updated non-reset invariant logical bus address for said destination node; and completing said bus transaction using said updated non-reset invariant logical bus address in place of said non-reset invariant logical bus address.
References Cited (Backward Citations)
US5394556A
Cited
US5579486A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |