US5764582A
Expired / Lapsed
US
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Apparatus and method of refreshing a dynamic random access memory
Assignee: Powerchip Technology Corp
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Filing: 1996-11-26
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Granted: 1998-06-09
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Expires: 2016-11-26
Abstract
Abstract A method and apparatus employing a power-saving technique to refresh data stored in an array of memory cells is disclosed. The refresh apparatus includes a latch circuit, where a reset signal is used to reset the latch circuit, and an input signal is provided change the state of the latch circuit. The refresh system also includes a circuit for generating a select signal electrically connected to the input of the latch circuit. The refresh further includes a pass circuit for passing a decoded signal to generate a selective refresh signal when the latch circuit is set, thereby refreshing one row of the memory cells which contains valid data (i.e., only after a write operation has occurred on the row in question).
Inventors
- 👤 Jy-Der David Tai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
An apparatus for refreshing data stored in an array of memory cells, said apparatus comprising: latch means, responsive to a reset signal and an input signal, for latching said input signal, said latch means being set to a first state by the reset signal; select means, responsive to a write signal and a memory access signal, for generating the input signal of said latch means, said latch means being set to a second state when both the write signal and the memory access signal become active, the second state or said latch means remaining until said latch means is reset to its first state by the reset signal; and means for passing said memory access signal to refresh the data stored in the array of the memory cells when said latch means is in the second state.
Claim 2
Independent Claim
137 words
An apparatus for refreshing data stored in an array of memory cells, said apparatus comprising: latch means, responsive to a reset signal and an input signal, for latching said input signal, said latch means being set to a first state by the reset signal; select means, responsive to a write signal and a memory access signal, for generating the input signal of said latch means, said latch means being set to a second state when both the write signal and the memory access signal become active, the second state or said latch means remaining until said latch means is reset to its first state by the reset signal; and means for passing said memory access signal to refresh the data stored in the array of the memory cells when said latch means is in the second state.
Claim 3
Dependent Claim
26 words
The apparatus according to claim 1, further comprising bitline means responsive to said passed memory access signal for controlling at least a bitline passgate control circuit.
Claim 4
Dependent Claim
25 words
The apparatus according to claim 2, wherein said bitline means comprises a circuit for pulling a first control signal to the bitline passgate control circuit.
Claim 5
Dependent Claim
26 words
The apparatus according to claim 1, further comprising amplifier-sense means responsive to said passed memory access signal for controlling at least a sense amplifier control circuit.
Claim 6
Dependent Claim
26 words
The apparatus according to claim 4, wherein said amplifier-sense means comprises a circuit for pulling down a second control signal to the sense amplifier control circuit.
Claim 7
Dependent Claim
24 words
The apparatus according to claim 1, wherein said input signal becomes active when both said write signal and said memory access signal are active.
Claim 8
Independent Claim
180 words
An apparatus for refreshing data stored in an array of memory cells, said apparatus comprising: a latch circuit configured to receive a reset signal and an input signal, said latch circuit being set to a first state when the reset signal becomes active; a select circuit configured to receive a write signal and a memory access signal, an output terminal of said select circuit being electrically connected to an input terminal of said latch circuit to provide the input signal of said latch circuit, said latch circuit being set to a second state when both the write signal and the memory access signal become active, the second state of said latch circuit remaining until said latch circuit is reset to its first state by the reset signal; and a passing circuit electrically connected to an output terminal of said latch circuit, and connected to receive the memory access signal, said memory access signal being passed through the passing circuit to refresh the data stored in the array of the memory cells when said latch circuit is in its second state.
Claim 9
Independent Claim
180 words
An apparatus for refreshing data stored in an array of memory cells, said apparatus comprising: a latch circuit configured to receive a reset signal and an input signal, said latch circuit being set to a first state when the reset signal becomes active; a select circuit configured to receive a write signal and a memory access signal, an output terminal of said select circuit being electrically connected to an input terminal of said latch circuit to provide the input signal of said latch circuit, said latch circuit being set to a second state when both the write signal and the memory access signal become active, the second state of said latch circuit remaining until said latch circuit is reset to its first state by the reset signal; and a passing circuit electrically connected to an output terminal of said latch circuit, and connected to receive the memory access signal, said memory access signal being passed through the passing circuit to refresh the data stored in the array of the memory cells when said latch circuit is in its second state.
Claim 10
Dependent Claim
31 words
The apparatus according to claim 7, further comprising means responsive to said passed memory access signal for pulling down a first control signal to at least a bitline passgate control circuit.
Claim 11
Dependent Claim
31 words
The apparatus according to claim 7, further comprising means responsive to said passed memory access signal for pulling down a second control signal to at least a sense amplifier control circuit.
Claim 12
Independent Claim
167 words
A method of refreshing data stored in an array of memory cells, said array being arranged in subsets of memory cells for which writing of data to the cells in the subset is controlled by a write signal, said method comprising the steps of: communicating a memory access signal to the cells of an associated subset as a function of the state of a latch circuit, wherein the memory access signal is communicated to the cells when the latch circuit is in a first state, and the memory access signal is inhibited from communicating to the cells when the latch circuit is in a second state; setting said latch circuit to its second state when both the write signal and the memory access signal become active, the second state of said latch circuit remaining until said latch circuit is reset to its first state; and refreshing the cells using the memory access signal, the cells being refreshed only when the latch circuit is in the second state.
Claim 13
Independent Claim
167 words
A method of refreshing data stored in an array of memory cells, said array being arranged in subsets of memory cells for which writing of data to the cells in the subset is controlled by a write signal, said method comprising the steps of: communicating a memory access signal to the cells of an associated subset as a function of the state of a latch circuit, wherein the memory access signal is communicated to the cells when the latch circuit is in a first state, and the memory access signal is inhibited from communicating to the cells when the latch circuit is in a second state; setting said latch circuit to its second state when both the write signal and the memory access signal become active, the second state of said latch circuit remaining until said latch circuit is reset to its first state; and refreshing the cells using the memory access signal, the cells being refreshed only when the latch circuit is in the second state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |