Method and apparatus for performing floating point addition

Claim 1

A method for performing a floating point addition comprising the steps of: receiving, in an exponent value processor, a first exponent value of a first operand from a first operand source and receiving a second exponent value of a second operand from a second operand source and calculating a plurality of candidate exponent result values substantially simultaneously; receiving, in a mantissa value processor, a first mantissa value of the first operand from the first operand source and receiving a second mantissa value of the second operand from the second operand source and calculating a plurality of candidate mantissa result values substantially simultaneously; receiving, in a control logic element, sign values of said first operand and of said second operand; receiving, in said control logic element, status outputs of the exponent value processor and of the mantissa value processor to generate status signals; and selecting, in said control logic element based on said status signals, from among said pluralities of candidate exponent result values and of said candidate mantissa result values to obtain a final exponent result value and a final mantissa result value, the selecting step of said control logic element comprising: examining said status signals including sign, exponent, and mantissa status signals; if said floating point operation is a true addition, and overflow is not indicated, then providing output of the exponent result and output the mantissa result via multiplexor means; if the operation is a true addition and an overflow is indicated, then providing the exponent result via an incrementor and providing the mantissa result via a right shifter; and if the operation is a true subtraction and exponents are not near in value, then performing a subtract via bit shifter means, sticky bit generator means, multiplexor means, adder/subtractor means, subtractor means, and left shifter means said bit shifter means, said sticky bit generator means, said multiplexor means, said adder/subtractor means, said subtractor means, and said left shifter means, being coupled in series for performing said subtract, the true subtraction operation further including the steps of: examining carry out signals from the adder/subtractor means and the subtractor means to determine which unit contains the positive difference of the mantissa; if the adder/subtractor means produces a positive result, and if an underflow is not detected, then providing the exponent result via the multiplexor means and providing the mantissa result via the adder/subtractor means; if the adder/subtractor means has a positive result and if it an underflow is detected, then providing the exponent result via a decrementor means and providing the mantissa result via the left shifter means; if the subtractor means has a positive result, and if no underflow is detected, then providing the exponent result via the multiplexor means and providing the mantissa result via the subtractor means; if subtractor means has a positive result, and if underflow is detected, then providing the exponent result via the decrementor means and providing the mantissa result via the left shifter means; and if the operation is a true subtraction and the subtractor means indicate that the exponents are near in value, then performing the subtract operation via shifter means, multiplexor means, and a leading zero predictor, said shifter means, said multiplexor means, and said leading zero predictor being coupled in series for the subtract operation.

Claim 2

A method for performing a floating point addition comprising the steps of: receiving, in an exponent value processor, a first exponent value of a first operand from a first operand source and receiving a second exponent value of a second operand from a second operand source and calculating a plurality of candidate exponent result values substantially simultaneously; receiving, in a mantissa value processor, a first mantissa value of the first operand from the first operand source and receiving a second mantissa value of the second operand from the second operand source and calculating a plurality of candidate mantissa result values substantially simultaneously; receiving, in a control logic element, sign values of said first operand and of said second operand; receiving, in said control logic element, status outputs of the exponent value processor and of the mantissa value processor to generate status signals; and selecting, in said control logic element based on said status signals, from among said pluralities of candidate exponent result values and of said candidate mantissa result values to obtain a final exponent result value and a final mantissa result value, the selecting step of said control logic element comprising: examining said status signals including sign, exponent, and mantissa status signals; if said floating point operation is a true addition, and overflow is not indicated, then providing output of the exponent result and output the mantissa result via multiplexor means; if the operation is a true addition and an overflow is indicated, then providing the exponent result via an incrementor and providing the mantissa result via a right shifter; and if the operation is a true subtraction and exponents are not near in value, then performing a subtract via bit shifter means, sticky bit generator means, multiplexor means, adder/subtractor means, subtractor means, and left shifter means said bit shifter means, said sticky bit generator means, said multiplexor means, said adder/subtractor means, said subtractor means, and said left shifter means, being coupled in series for performing said subtract, the true subtraction operation further including the steps of: examining carry out signals from the adder/subtractor means and the subtractor means to determine which unit contains the positive difference of the mantissa; if the adder/subtractor means produces a positive result, and if an underflow is not detected, then providing the exponent result via the multiplexor means and providing the mantissa result via the adder/subtractor means; if the adder/subtractor means has a positive result and if it an underflow is detected, then providing the exponent result via a decrementor means and providing the mantissa result via the left shifter means; if the subtractor means has a positive result, and if no underflow is detected, then providing the exponent result via the multiplexor means and providing the mantissa result via the subtractor means; if subtractor means has a positive result, and if underflow is detected, then providing the exponent result via the decrementor means and providing the mantissa result via the left shifter means; and if the operation is a true subtraction and the subtractor means indicate that the exponents are near in value, then performing the subtract operation via shifter means, multiplexor means, and a leading zero predictor, said shifter means, said multiplexor means, and said leading zero predictor being coupled in series for the subtract operation.