Semiconductor module for microprocessor

Claim 2

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a first surface supporting a plurality of terminals to be connected when the semiconductor package is mounted on a wiring board, said first surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a second surface of said plastic grid array package, opposite to said first surface which supports said terminals; and heat-radiating means covering all of said plurality of cache memories and mounted on said surface on which said cache memories are mounted, at a position corresponding to said recess, for radiating heat generated by said plurality of cache memories and said microprocessor semiconductor device.

Claim 3

A semiconductor package according to claim 1, wherein said recess is defined by a through hole defined in said plastic grid array package and a metal plate having a top surface substantially coincident with the second surface of said plastic grid array package, closing said through hole at said second surface on which said cache memories are mounted, said heat-radiating means being mounted on said metal plate.

Claim 4

A semiconductor package according to claim 1, wherein said recess is defined centrally in said plastic grid array package, said cache memories being disposed in surrounding relationship to said recess.

Claim 5

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals comprising conductive balls to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; and a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; said surface on which said cache memories are mounted including a portion corresponding to said recess, said portion serving as a region for installing heat-radiating means which covers all of said plurality of cache memories and operates for radiating heat generated by said plurality of cache memories and said microprocessor semiconductor device.

Claim 6

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals comprising conductive balls to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; and a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; said surface on which said cache memories are mounted including a portion corresponding to said recess, said portion serving as a region for installing heat-radiating means which covers all of said plurality of cache memories and operates for radiating heat generated by said plurality of cache memories and said microprocessor semiconductor device.

Claim 7

A semiconductor package according to claim 4, wherein said recess is defined by a through hole defined in said plastic grid array package and a metal plate closing said through hole at said surface on which said cache memories are mounted, said heat-radiating means being mounted on said metal plate.

Claim 8

A semiconductor package according to claim 4, wherein said recess is defined centrally in said plastic grid array package, said cache memories being disposed in surrounding relationship to said recess.

Claim 9

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a first surface; a microprocessor semiconductor device mounted on said first surface; a heat sink mounted on a second surface of said plastic grid array package opposite to said first surface; said heat sink having a plurality of fins spaced from said second surface by a gap; and a plurality of cache memories mounted on said second surface, each and every one of said plurality of cache memories disposed in said gap in spaced relationship to each other.

Claim 10

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a first surface; a microprocessor semiconductor device mounted on said first surface; a heat sink mounted on a second surface of said plastic grid array package opposite to said first surface; said heat sink having a plurality of fins spaced from said second surface by a gap; and a plurality of cache memories mounted on said second surface, each and every one of said plurality of cache memories disposed in said gap in spaced relationship to each other.

Claim 11

A semiconductor package according to claim 1, wherein said heat-radiating means has a single leg which attaches said heat-radiating means to said second surface of said plastic grid array package at a location substantially adjacent to said microprocessor semiconductor.

Claim 12

A semiconductor package according to claim 8, wherein said cache memories are disposed in surrounding relationship to said recess and in substantially equidistantly spaced relationship to said microprocessor semiconductor device to thereby allow said microprocessor to operate at a high frequency substantially equal to the frequency of said plurality of cache memories.

Claim 13

A semiconductor package according to claim 9, whereby said plastic pin grid array has a thermal expansion co-efficient substantially equal to each of said plurality of cache memories comprised of a ball grid array package.

Claim 14

A semiconductor package according to claim 10, wherein said plurality of terminals are pins.

Claim 15

A semiconductor package according to claim 10, wherein said plurality of terminals are balls.

Claim 16

A semiconductor package according to claim 10, wherein said plurality of terminals are pads.

Claim 17

A semiconductor package according to claim 10, wherein said plurality of terminals are columns of solder.

Claim 18

A semiconductor package according to claim 1, wherein said plastic grid array package comprises a composite substrate composed of glass fiber cloth and an organic material.

Claim 19

A semiconductor package according to claim 15, wherein said cache memories ball grid array package comprises a composite substrate composed of glass fiber cloth and an organic material.

Claim 20

A semiconductor package according to claim 7, wherein said plastic grid array package comprises a composite substrate composed of glass fiber cloth and an organic material.

Claim 21

A semiconductor package according to claim 17, wherein said cache memories comprises a composite substrate composed of glass fiber cloth and an organic material.

Claim 22

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; and heat-radiating means mounted on said surface on which said cache memories are mounted, at a position corresponding to said recess, for radiating heat generated by said microprocessor semiconductor device.

Claim 23

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; and heat-radiating means mounted on said surface on which said cache memories are mounted, at a position corresponding to said recess, for radiating heat generated by said microprocessor semiconductor device.

Claim 24

A semiconductor package according to claim 19, wherein said recess is defined by a through hole defined in said plastic grid array package and a metal plate closing said through hole at said surface on which said cache memories are mounted, said heat-radiating means being mounted on said metal plate.

Claim 25

A semiconductor package according to claim 19, wherein said recess is defined centrally in said plastic grid array package, said cache memories being disposed in surrounding relationship to said recess.

Claim 26

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals comprising conductive balls to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; and a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; said surface on which said cache memories are mounted including a portion corresponding to said recess, said portion servicing as a region for installing heat-radiating means for radiating heat generated by said microprocessor semiconductor device, after said terminals are connected to the wiring board.

Claim 27

A semiconductor package for a microprocessor, comprising: a plastic grid array package including a surface supporting a plurality of terminals comprising conductive balls to be connected when the semiconductor package is mounted on a wiring board, said surface having a recess defined therein; a microprocessor semiconductor device housed in said recess; and a plurality of cache memories each comprising a ball grid array package, said cache memories being mounted on a surface of said plastic grid array package opposite to said surface which supports said terminals; said surface on which said cache memories are mounted including a portion corresponding to said recess, said portion servicing as a region for installing heat-radiating means for radiating heat generated by said microprocessor semiconductor device, after said terminals are connected to the wiring board.

Claim 28

A semiconductor package according to claim 22, wherein said recess is defined by a through hole defined in said plastic grid array package and a metal plate closing said through hole at said surface on which said cache memories are mounted, said heat-radiating means being mounted on said metal plate.

Claim 29

A semiconductor package according to claim 22, wherein said recess is defined centrally in said plastic grid array package, said cache memories being disposed in surrounding relationship to said recess.

Claim 30

A semiconductor package for a microprocessor comprising: a plastic grid array package including a first surface; a microprocessor semiconductor device mounted on said surface; a heat sink mounted on a second surface of said plastic grid array package opposite to said first surface; said heat sink having a plurality of fins spaced from said second surface by a gap; and a plurality of cache memories mounted on said second surface and disposed in said gap in spaced relationship to each other.

Claim 31

A semiconductor package for a microprocessor comprising: a plastic grid array package including a first surface; a microprocessor semiconductor device mounted on said surface; a heat sink mounted on a second surface of said plastic grid array package opposite to said first surface; said heat sink having a plurality of fins spaced from said second surface by a gap; and a plurality of cache memories mounted on said second surface and disposed in said gap in spaced relationship to each other.