Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
122 words
An improved graphics processor of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine, the buffer also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine, wherein the improvement comprises: (a) a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer; (b) means for providing user access via an application only to the normal FIFO; and (c) means for providing system level code access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor.
Claim 2
Dependent Claim
122 words
An improved graphics processor of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine, the buffer also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine, wherein the improvement comprises: (a) a plurality of logical FIFOs, including a normal FIFO and a protected FIFO, having addresses all mapping to the same physical graphics FIFO buffer; (b) means for providing user access via an application only to the normal FIFO; and (c) means for providing system level code access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor.
Claim 3
Dependent Claim
64 words
A processor according to claim 1, further comprising: a logical sync FIFO, in addition to the normal FIFO and the protected FIFO, having an address mapping to the same physical graphics FIFO buffer; and means for using the sync FIFO in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing.
Claim 4
Independent Claim
140 words
A method of controlling a graphics processor of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine, the buffer also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine, the method comprising: (a) causing the graphics FIFO buffer to have a plurality of logical addresses, including a normal address and a protected address, all mapping to this same physical buffer, so as to create a plurality of logical FIFOs including a normal FIFO and a protected FIFO; (b) providing user access via an application only to the normal FIFO; and (c) providing system level code access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor.
Claim 5
Independent Claim
140 words
A method of controlling a graphics processor of the type having a graphics engine and a graphics FIFO buffer in communication with the graphics engine, the buffer also in communication with a host processor over a bus so as to provide request code and data from the host processor to the graphics engine, the method comprising: (a) causing the graphics FIFO buffer to have a plurality of logical addresses, including a normal address and a protected address, all mapping to this same physical buffer, so as to create a plurality of logical FIFOs including a normal FIFO and a protected FIFO; (b) providing user access via an application only to the normal FIFO; and (c) providing system level code access to all of the logical FIFOs, so that the protected FIFO can be used for control of the graphics processor.
Claim 6
Dependent Claim
74 words
A method according to claim 3, wherein step (a) includes the step of causing the graphics FIFO buffer to have a sync address so as to create a logical sync FIFO, in addition to the normal FIFO and the protected FIFO, the method further comprising: (d) using the sync FIFO in error recovery to receive and store a request that can be detected by the graphics engine as a cue to restart normal processing.