Process for fabricating memory cells of flash memory

Claim 1

A process for fabricating memory cells of a flash memory device, comprising the steps of: a. providing a silicon substrate; b. forming a tunnel oxide layer on the silicon substrate, and then forming a first polysilicon layer on top of the tunnel oxide layer; c. successively forming a dielectric layer, a second polysilicon layer, and a silicide layer on top of the first polysilicon layer and the tunnel oxide layer; d. forming a control gate shielding mask on a surface of the silicide layer, so as to partially cover the tunnel oxide layer, with one edge of the mask aligned with one edge of the tunnel oxide layer; e. performing an etching procedure utilizing the control gate shielding mask, to partially remove the silicide layer, the second polysilicon layer, the dielectric layer and the first polysilicon layer, so as to form a control gate layer and a floating gate layer, and expose an unshielded region on one side of the tunnel oxide layer; f. implanting first impurities in the silicon substrate by a first ion implantation procedure, to form a source region and a drain region on the silicon substrate, the source region being adjacent to the unshielded region of the tunnel oxide layer; g. forming oxide sidewall spacers on sidewalls of the control gate layer, a remaining portion of the dielectric layer, the floating gate layer, and the unexposed region of the tunneling gate layer; and h. implanting a second impurity in the substrate by an ion implantation procedure, at an incident angle of about 30 to 40 degrees, to form a lightly-doped source region in the silicon substrate under the unshielded region of the tunnel oxide layer.