Method and system for emulating instructions by performing an operation directly using special-purpose register contents

Claim 3

A method as in claim 1 wherein the processor includes an emulation assist unit, wherein step (a) includes that step of: (a1) providing the special-purpose register in the emulation assist unit.

Claim 4

A method as in claim 2 wherein the processor includes an arithmetic logical unit and a multiplexer, wherein the arithmetic logical unit is coupled between the general purpose register and the multiplexer, wherein step (a) further includes the step of: (a2) coupling the special-purpose register to the arithmetic logical unit.

Claim 5

A method as in claim 3 wherein step (b) further includes the step of: (b1) storing the result of the operation in a third general purpose register.

Claim 6

A method as in claim 4 wherein the operation is an arithmetic operation.

Claim 7

A method as in claim 5 wherein the operation is a data transfer operation.

Claim 8

A method as in claim 6 wherein the operation is a logic operation.

Claim 9

A method as in claim 7 wherein the processor emulates the guest instruction using an semantic routine and the instruction is an instruction within the semantic routine.

Claim 10

A processor for emulating a guest instruction, the guest instruction including a first operand and a second operand, the processor comprising: means for storing the first operand in a general purpose register and the second operand in a special-purpose register; and instruction means that perform an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register.

Claim 11

A processor for emulating a guest instruction, the guest instruction including a first operand and a second operand, the processor comprising: means for storing the first operand in a general purpose register and the second operand in a special-purpose register; and instruction means that perform an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register.

Claim 12

A processor as in claim 9 wherein the processor further includes an emulation assist unit, and wherein the special-purpose register is part of the emulation assist unit.

Claim 13

A processor as in claim 10 wherein the processor further includes: an arithmetic logical unit; and a multiplexer, wherein the arithmetic logical unit is coupled between the general purpose register and the multiplexer, and wherein the special-purpose register is coupled to the arithmetic logical unit.

Claim 14

A processor as in claim 11 wherein the instruction means further includes means for storing the result of the operation in a third general purpose register.

Claim 15

A processor as in claim 12 wherein the instruction means is an arithmetic operation.

Claim 16

A processor as in claim 13 wherein the instruction means is a data transfer operation.

Claim 17

A processor as in claim 14 wherein the instruction means is a logic operation.

Claim 18

A processor as in claim 15 wherein the processor emulates the guest instruction using an semantic routine and the instruction means is an instruction within the semantic routine.

Claim 19

A processor for emulating guest instructions, wherein a plurality of the guest instructions include immediate data, the processor comprising: a memory for storing semantic routines at specific addresses, each of the semantic routines including a block of host instructions for emulating the function of the guest instructions; an emulation assist unit for decoding guest instructions and dispatching a corresponding semantic routine, the emulation assist unit including, a plurality of special-purpose registers for storing a plurality of entries, wherein each of the plurality of entries includes an offset field and a data field, wherein the offset field is a pointer to the memory address the semantic routine, and the data field is the immediate data from the corresponding guest instruction; a plurality of general-purpose registers for storing operands; and a plurality of host instructions in the semantic routines that perform operations using the immediate data and the operands in the general-purpose registers without moving the immediate data from the special-purpose registers into the general-purpose registers.

Claim 20

A processor for emulating guest instructions, wherein a plurality of the guest instructions include immediate data, the processor comprising: a memory for storing semantic routines at specific addresses, each of the semantic routines including a block of host instructions for emulating the function of the guest instructions; an emulation assist unit for decoding guest instructions and dispatching a corresponding semantic routine, the emulation assist unit including, a plurality of special-purpose registers for storing a plurality of entries, wherein each of the plurality of entries includes an offset field and a data field, wherein the offset field is a pointer to the memory address the semantic routine, and the data field is the immediate data from the corresponding guest instruction; a plurality of general-purpose registers for storing operands; and a plurality of host instructions in the semantic routines that perform operations using the immediate data and the operands in the general-purpose registers without moving the immediate data from the special-purpose registers into the general-purpose registers.

Claim 21

A processor as in claim 17 wherein the processor further includes an integer unit for executing the host instructions, the integer unit including an arithmetic logical unit and a multiplexer, wherein the arithmetic logical unit is coupled between the plurality of general-purpose registers and the multiplexer, and wherein the special-purpose registers are coupled to the arithmetic logical unit.