Patent US5758135A successfully refreshed from Google Patents.
US5758135A
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System and method for fast clocking a digital display in a multiple concurrent display system
Assignee: Seiko Epson Corp
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Filing: 1996-09-24
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Granted: 1998-05-26
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Expires: 2016-09-24
Abstract
Abstract A clocking system including a line clock system for generating normal line clock pulses to the digital display during the period when the image is being rendered and for generating fast line clock pulses to the digital display during the vertical blanking period to address the otherwise unaddressed vertical region. The clocking system further includes a pixel clock system for generating normal pixel clock pulses to the digital display during the period when the image is being rendered and for generating fast pixel clock pulses to the digital display during the horizontal and vertical blanking periods to address the otherwise unaddressed horizontal and vertical regions.
Inventors
- 👤 David M. Tucker
- 👤 William Low
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:16
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G09; G09G; G09G5/00; G09G5/003; G09G5/005; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G5/36; G09G5/363; G09G5/366; G09G2310/00; G09G2310/02; G09G2310/0232; G09G2340/00; G09G2340/04; G09G5/006; G09G5/18
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
137 words
A display clocking system, comprising: a line clock selector having first and second line clock input terminals for receiving first and second line clock signals, a line clock control terminal and a line clock output terminal for transmitting a selected one of the first and second line clock signals; a first line clock coupled to the first line clock input terminal for generating the first line clock signal; a second line clock coupled to the second line clock input terminal for generating the second line clock signal having, a higher frequency than the first line clock signal; and a line clock controller coupled to the line clock control terminal for generating a control signal to select the first line clock signal during an image rendering period and the second line clock signal during a horizontal blanking period.
Claim 2
Dependent Claim
137 words
A display clocking system, comprising: a line clock selector having first and second line clock input terminals for receiving first and second line clock signals, a line clock control terminal and a line clock output terminal for transmitting a selected one of the first and second line clock signals; a first line clock coupled to the first line clock input terminal for generating the first line clock signal; a second line clock coupled to the second line clock input terminal for generating the second line clock signal having, a higher frequency than the first line clock signal; and a line clock controller coupled to the line clock control terminal for generating a control signal to select the first line clock signal during an image rendering period and the second line clock signal during a horizontal blanking period.
Claim 3
Dependent Claim
101 words
The system of claim 1 wherein the line clock selector comprises: a line multiplexer having a first input terminal connected to the first line clock, a second input terminal connected to the second line clock, an output terminal connected to a digital display, and a control terminal for controlling which one of the clock signals passes to the output terminal; and control logic connected to the control terminal enabling the first line clock signal to pass to the output terminal during an image rendering period and the second line clock to pass to the output terminal during a vertical blanking period.
Claim 4
Dependent Claim
34 words
The system of claim 1, wherein the second line clock speed is a function of the number of lines between a vertical dimension of the image and a digital display scan size vertical dimension.
Claim 5
Dependent Claim
137 words
A display clocking system, comprising: a pixel clock selector having first and second pixel clock input terminals for receiving first and second pixel clock signals, a pixel clock control terminal and a pixel clock output terminal for transmitting a selected one of the first and second pixel clock signals; a first pixel clock coupled to the first pixel clock input terminal for generating the first pixel clock signal; a second pixel clock coupled to the second pixel clock input terminal for generating the second pixel clock signal having a higher frequency than the first pixel clock signal; and a pixel clock controller coupled to the pixel clock control terminal for generating a control signal to select the first pixel clock signal during the image rendering period and the second pixel clock signal during a vertical blanking period.
Claim 6
Dependent Claim
137 words
A display clocking system, comprising: a pixel clock selector having first and second pixel clock input terminals for receiving first and second pixel clock signals, a pixel clock control terminal and a pixel clock output terminal for transmitting a selected one of the first and second pixel clock signals; a first pixel clock coupled to the first pixel clock input terminal for generating the first pixel clock signal; a second pixel clock coupled to the second pixel clock input terminal for generating the second pixel clock signal having a higher frequency than the first pixel clock signal; and a pixel clock controller coupled to the pixel clock control terminal for generating a control signal to select the first pixel clock signal during the image rendering period and the second pixel clock signal during a vertical blanking period.
Claim 7
Dependent Claim
101 words
The system of claim 4 wherein the pixel clock selector comprises: a pixel multiplexer having a first input terminal connected to the first pixel clock, a second input terminal connected to the fast pixel clock, an output terminal connected to a digital display, and a control terminal for controlling which one of the pixel clock signals passes to the output terminal; and control logic connected to the control terminal enabling the first pixel clock signal to pass to the output terminal during an image rendering period and the second pixel clock to pass to the output terminal during vertical blanking period.
Claim 8
Dependent Claim
32 words
The system of claim 4, wherein the second pixel clock speed is a function of the difference between a horizontal dimension of the image and a digital display scan size horizontal dimension.
Claim 9
Independent Claim
278 words
A system for fast clocking a digital display, comprising: a line clock selector having first and second line clock input terminals for receiving first and second line clock signals, a line clock control terminal and a line clock output terminal for transmitting a selected one of the first and second line clock signals; a first line clock coupled to the first line clock input terminal for generating the first line clock signal; a second line clock coupled to the second line clock input terminal for generating the second line clock signal having a higher frequency than the first line clock signal; a line clock controller coupled to the line clock control terminal for generating a control signal to select the first line clock signal during an image rendering period and the second line clock signal during a horizontal blanking period; a pixel clock selector having first and second pixel clock input terminals for receiving first and second pixel clock signals, a pixel clock control terminal and a pixel clock output terminal for transmitting a selected one of the first and second pixel clock signals; a first pixel clock coupled to the first pixel clock input terminal for generating the first pixel clock signal; a second pixel clock coupled to the second pixel clock input terminal for generating the second pixel clock signal having a higher frequency than the first pixel clock signal; and a pixel clock controller coupled to the pixel clock control terminal for generating a control signal to select the first pixel clock signal during the image rendering period and the second pixel clock signal during both the horizontal blanking period and a vertical blanking period.
Claim 10
Independent Claim
278 words
A system for fast clocking a digital display, comprising: a line clock selector having first and second line clock input terminals for receiving first and second line clock signals, a line clock control terminal and a line clock output terminal for transmitting a selected one of the first and second line clock signals; a first line clock coupled to the first line clock input terminal for generating the first line clock signal; a second line clock coupled to the second line clock input terminal for generating the second line clock signal having a higher frequency than the first line clock signal; a line clock controller coupled to the line clock control terminal for generating a control signal to select the first line clock signal during an image rendering period and the second line clock signal during a horizontal blanking period; a pixel clock selector having first and second pixel clock input terminals for receiving first and second pixel clock signals, a pixel clock control terminal and a pixel clock output terminal for transmitting a selected one of the first and second pixel clock signals; a first pixel clock coupled to the first pixel clock input terminal for generating the first pixel clock signal; a second pixel clock coupled to the second pixel clock input terminal for generating the second pixel clock signal having a higher frequency than the first pixel clock signal; and a pixel clock controller coupled to the pixel clock control terminal for generating a control signal to select the first pixel clock signal during the image rendering period and the second pixel clock signal during both the horizontal blanking period and a vertical blanking period.
Claim 11
Dependent Claim
102 words
The system of claim 7 wherein the line clock selector comprises: a line multiplexer having a first input terminal connected to the first line clock, a second input terminal connected to the second line clock, an output terminal connected to the digital display, and a control terminal for controlling which one of said line clock signals passes to the output terminal; and control logic connected to the control terminal enabling the first line clock signal to pass to the output terminal during an image rendering period and the second line clock to pass to the output terminal during a vertical blanking period.
Claim 12
Dependent Claim
103 words
The system of claim 7 wherein the pixel clock selector comprises: a pixel multiplexer having a first input terminal connected to the first pixel clock, a second input terminal connected to the fast pixel clock, an output terminal connected to the digital display, and a control terminal for controlling which one of said pixel clock signals passes to the output terminal; and control logic connected to the control terminal enabling the first pixel clock signal to pass to the output terminal during an image rendering period and the second pixel clock to pass to the output terminal during horizontal and vertical blanking periods.
Claim 13
Dependent Claim
116 words
The system of claim 7, wherein the digital display is an N-pixel-by-M-line display; wherein the first line clock speed and the first pixel clock speed are based on an A-pixel-by-B-line display having an image size of C pixels by D lines; wherein the system handles only one pixel per pixel clock pulse; and wherein the speeds of the second line clock and of the second pixel clock are computed according to the equations ##EQU3## where T HF is the period of a second pixel clock, T HC is the period of a first pixel clock, T VF is the period of a second line clock and T VC is the period of a first line clock.
Claim 14
Dependent Claim
61 words
The system of claim 7, wherein the second line clock speed is a function of the number of lines between a vertical dimension of the image and a digital display scan size vertical dimension, and the second pixel clock speed is a function of the difference between a horizontal dimension of the image and a digital display scan size horizontal dimension.
Claim 15
Independent Claim
70 words
A system for fast clocking a digital display, comprising: means for generating a first line clock signal; means for generating a second line clock signal having a higher frequency than the first line clock signal; means for selecting the first line clock to drive the digital display during an image rendering period; and means for selecting the second line clock signal to drive the display during a horizontal blanking period.
Claim 16
Independent Claim
70 words
A system for fast clocking a digital display, comprising: means for generating a first line clock signal; means for generating a second line clock signal having a higher frequency than the first line clock signal; means for selecting the first line clock to drive the digital display during an image rendering period; and means for selecting the second line clock signal to drive the display during a horizontal blanking period.
Claim 17
Independent Claim
70 words
A system for fast clocking a digital display, comprising: means for generating a first pixel clock signal; means for generating a second pixel clock signal having a higher frequency than the first pixel clock signal; means for selecting the first pixel clock to drive the digital display during an image rendering period; and means for selecting the second pixel clock signal to drive the display during a vertical blanking period.
Claim 18
Independent Claim
70 words
A system for fast clocking a digital display, comprising: means for generating a first pixel clock signal; means for generating a second pixel clock signal having a higher frequency than the first pixel clock signal; means for selecting the first pixel clock to drive the digital display during an image rendering period; and means for selecting the second pixel clock signal to drive the display during a vertical blanking period.
Claim 19
Independent Claim
65 words
A method of fast clocking a digital display, comprising the steps of: generating a first line clock signal; generating a second line clock signal having a higher frequency than the first line clock signal; selecting the first line clock to drive the digital display during an image rendering period; and selecting the second line clock signal to drive the display during a horizontal blanking period.
Claim 20
Independent Claim
65 words
A method of fast clocking a digital display, comprising the steps of: generating a first line clock signal; generating a second line clock signal having a higher frequency than the first line clock signal; selecting the first line clock to drive the digital display during an image rendering period; and selecting the second line clock signal to drive the display during a horizontal blanking period.
Claim 21
Dependent Claim
34 words
The method of claim 14, wherein the second line clock speed is a function of the number of lines between a vertical dimension of the image and a digital display scan size vertical dimension.
Claim 22
Independent Claim
65 words
A method of fast clocking a digital display, comprising the steps of: generating a first pixel clock signal; generating a second pixel clock signal having a higher frequency than the first pixel clock signal; selecting the first pixel clock to drive the digital display during an image rendering period; and selecting the second pixel clock signal to drive the display during a vertical blanking period.
Claim 23
Independent Claim
65 words
A method of fast clocking a digital display, comprising the steps of: generating a first pixel clock signal; generating a second pixel clock signal having a higher frequency than the first pixel clock signal; selecting the first pixel clock to drive the digital display during an image rendering period; and selecting the second pixel clock signal to drive the display during a vertical blanking period.
Claim 24
Dependent Claim
32 words
The method of claim 16, wherein the second pixel clock speed is a function of the difference between a horizontal dimension of the image and a digital display scan size horizontal dimension.
Claim 25
Independent Claim
124 words
A method of fast clocking a digital display, comprising the steps of: generating a first line clock signal; generating a second line clock signal having a higher frequency than the first line clock signal; selecting the first line clock to drive the digital display during an image rendering period; selecting the second line clock signal to drive the display during a horizontal blanking period; generating a first pixel clock signal; generating a second pixel clock signal having a higher frequency than the first pixel clock signal; selecting the first pixel clock signal to drive the digital display during an image rendering period; and selecting the second pixel clock signal to drive the display during both the horizontal blanking period and a vertical blanking period.
Claim 26
Independent Claim
124 words
A method of fast clocking a digital display, comprising the steps of: generating a first line clock signal; generating a second line clock signal having a higher frequency than the first line clock signal; selecting the first line clock to drive the digital display during an image rendering period; selecting the second line clock signal to drive the display during a horizontal blanking period; generating a first pixel clock signal; generating a second pixel clock signal having a higher frequency than the first pixel clock signal; selecting the first pixel clock signal to drive the digital display during an image rendering period; and selecting the second pixel clock signal to drive the display during both the horizontal blanking period and a vertical blanking period.
Claim 27
Dependent Claim
117 words
The method of claim 18, wherein the digital display is an N-pixel-by-M-line display; wherein the first line clock speed and the first pixel clock speed are computed based on an A-pixel-by-B-line display with an image size of C pixels by D lines wherein the system handles only one pixel per pixel clock pulse; and wherein the speeds of the second line clock and of the second pixel clock are computed according to the equations ##EQU4## where T HF is the period of a second pixel clock, T HC is the period of a first pixel clock, T VF is the period of a second line clock and T VC is the period of a first line clock.
Claim 28
Dependent Claim
61 words
The method of claim 18, wherein the second line clock speed is a function of the number of lines between a vertical dimension of the image and a digital display scan size vertical dimension, and the second pixel clock speed is a function of the difference between a horizontal dimension of the image and a digital display scan size horizontal dimension.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |