Patent US5757873A successfully refreshed from Google Patents.
US5757873A
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Differential delay buffer
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-06-06
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Granted: 1998-05-26
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Expires: 2015-06-06
Abstract
Abstract A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay buffer units can be cascaded together, in each variable delay buffer units a part of the required delay being effected. The variable hysteresis stage is responsive to the signal level at a second differential stage output to recover the signal at a first differential signal output from the variable delay buffer unit and is responsive to the signal level at a first differential stage output to recover the signal at the second delayed differential signal output for the variable delay buffer unit. The differential delay buffer can be included in a delay locked loop in data transmission applications.
Inventors
- 👤 Kenneth Stephen Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:44
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
193 words
A differential variable delay buffer, comprising: a variable delay buffer unit, said variable delay buffer having first and second differential signal inputs and first and second delayed differential signal outputs, wherein said variable delay buffer unit comprises: a differential stage, said differential stage having first and second differential stage inputs connected to said first and second differential signal inputs and first and second differential stare outputs connected to said first and second delayed differential signal outputs: and a variable hysteresis stage, said variable hysteresis stage following said differential stage and controlling signal delay in said variable delay buffer unit, said variable hysteresis stage connected between said first and second differential stage outputs and said first and second delayed differential signal outputs, said variable hysteresis stage having a first recovery transistor connected between said first delayed differential signal output and a first variable current source, a gate of said first recovery transistor being connected to said second differential stage output, and a second recovery transistor connected between said second delayed differential signal output and a second variable current source, a gate of said second recovery transistor being connected to said first differential stage output.
Claim 2
Dependent Claim
193 words
A differential variable delay buffer, comprising: a variable delay buffer unit, said variable delay buffer having first and second differential signal inputs and first and second delayed differential signal outputs, wherein said variable delay buffer unit comprises: a differential stage, said differential stage having first and second differential stage inputs connected to said first and second differential signal inputs and first and second differential stare outputs connected to said first and second delayed differential signal outputs: and a variable hysteresis stage, said variable hysteresis stage following said differential stage and controlling signal delay in said variable delay buffer unit, said variable hysteresis stage connected between said first and second differential stage outputs and said first and second delayed differential signal outputs, said variable hysteresis stage having a first recovery transistor connected between said first delayed differential signal output and a first variable current source, a gate of said first recovery transistor being connected to said second differential stage output, and a second recovery transistor connected between said second delayed differential signal output and a second variable current source, a gate of said second recovery transistor being connected to said first differential stage output.
Claim 3
Dependent Claim
45 words
The buffer according to claim 1 wherein said first and second variable current sources are formed by a current source transistor connected between said recovery transistors and first voltage supply a gate of said current supply transistor being connected to receive a delay control signal.
Claim 4
Dependent Claim
23 words
The buffer according to claim 2, wherein said first and second variable current sources are formed by a common first current source transistor.
Claim 5
Dependent Claim
131 words
A differential variable delay buffer, comprising: a variable delay buffer unit, wherein said variable delay buffer unit comprises; a differential stage, said differential stage comprises a first comparator transistor having a gate connected to a first differential signal input and a second comparator transistor having a gate connected to a second differential signal input, said first comparator transistor being connected via a second current source transistor to a second voltage supply, said second comparator transistor being connected via a third current source transistor to said second voltage supply and said first and second comparator transistors being connected via a fourth current source transistor to a first voltage supply; and a variable hysteresis stage, said variable hysteresis stage following said differential stage and controlling signal delay in said variable delay buffer unit.
Claim 6
Dependent Claim
131 words
A differential variable delay buffer, comprising: a variable delay buffer unit, wherein said variable delay buffer unit comprises; a differential stage, said differential stage comprises a first comparator transistor having a gate connected to a first differential signal input and a second comparator transistor having a gate connected to a second differential signal input, said first comparator transistor being connected via a second current source transistor to a second voltage supply, said second comparator transistor being connected via a third current source transistor to said second voltage supply and said first and second comparator transistors being connected via a fourth current source transistor to a first voltage supply; and a variable hysteresis stage, said variable hysteresis stage following said differential stage and controlling signal delay in said variable delay buffer unit.
Claim 7
Dependent Claim
16 words
The buffer according to claim 2, wherein said first voltage supply is a 0volt supply line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |