Method of decoupling the high order portion of the addend from the multiply result in an FMAC

Claim 2

A floating-point multiply accumulate unit (FMAC) for performing the accumulate operation (A*B)+C, wherein each of inputs A, B and C comprise a mantissa and an exponent, and wherein a multiply unit places an (A*B) mantissa in an (A*B) register, the unit comprising: a) a CHI register, coupled to means for transferring bits of the C mantissa which exceed a range of the (A*B) mantissa to the CHI register; b) a CBUS register, coupled to a first shifter for placing bits of the C mantissa which overlap the range of the (A*B) mantissa into the CBUS register, the overlapping bits of the mantissas contained within the (A*B) and CBUS registers being aligned for adding; c) an adder, coupled to the (A*B) and CBUS registers, and providing an (A*B)+CBUS output; d) a leading bit anticipator connected to the (A*B)+CBUS output of the adder; e) a second shifter, coupled to the leading bit anticipator, and providing a temporary output; and f) means for merging those bits of the CHI register comprising bits of the C mantissa which exceed the range of the (A*B) mantissa with one or more most significant bits of the temporary output to produce an (A*B)+C accumulate output.

Claim 3

An FMAC as in claim 1, wherein: a) the A×B mantissa comprises "2m+1"-bits; b) the (A*B)+CBUS output comprises "2m+1"-bits; and c) the adder has a maximum width of "2m+1"-bits.

Claim 4

An FMAC as in claim 2, wherein the first and second shifters have maximum widths of "2m+1"-bits.

Claim 5

An FMAC as in claim 3, wherein the leading bit anticipator has a maximum width of "2m+1"-bits.

Claim 6

An FMAC as in claim 4, wherein the FMAC has a mantissa datapath width of "2m+1"-bits.

Claim 7

In a floating-point multiply accumulate unit for performing the accumulate operation (A*B)+C, wherein A, B, and C each comprise an m-bit mantissa and an exponent, and an (A*B) result comprises a "2m+1"-bit mantissa and an exponent, a method of adding C to the (A*B) result, comprising the steps of: a) comparing the exponents of (A*B) and C to determine whether there is an overlapping range of the (A*B) and C mantissas; b) transferring any part of the C mantissa which exceeds a range of the (A*B) mantissa to a CHI register; c) shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa, so as to align the bits of the (A*B) and C mantissas according to their respective magnitudes; d) adding the shifted part of the C mantissa to the (A*B) mantissa to generate a temporary result; e) if a portion of the C mantissa was transferred to the CHI register, shifting one or more least significant bits corresponding to a number of bits transferred to the CHI register out of the temporary result; and f) merging the bits of the C mantissa which were transferred to the CHI register with one or more most significant bit positions of the temporary result to generate an accumulate result.

Claim 8

In a floating-point multiply accumulate unit for performing the accumulate operation (A*B)+C, wherein A, B, and C each comprise an m-bit mantissa and an exponent, and an (A*B) result comprises a "2m+1"-bit mantissa and an exponent, a method of adding C to the (A*B) result, comprising the steps of: a) comparing the exponents of (A*B) and C to determine whether there is an overlapping range of the (A*B) and C mantissas; b) transferring any part of the C mantissa which exceeds a range of the (A*B) mantissa to a CHI register; c) shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa, so as to align the bits of the (A*B) and C mantissas according to their respective magnitudes; d) adding the shifted part of the C mantissa to the (A*B) mantissa to generate a temporary result; e) if a portion of the C mantissa was transferred to the CHI register, shifting one or more least significant bits corresponding to a number of bits transferred to the CHI register out of the temporary result; and f) merging the bits of the C mantissa which were transferred to the CHI register with one or more most significant bit positions of the temporary result to generate an accumulate result.

Claim 9

A method as in claim 6, wherein the temporary result comprises a "2m+1"-bit mantissa.

Claim 10

A method as in claim 7, further comprising the step of truncating the accumulate result so as to create an "m-1"-bit accumulate result.

Claim 11

A method as in claim 8, wherein the step of truncating the accumulate result is performed simultaneously with the step of merging the bits of the C mantissa which were transferred to the CHI register with one or more most significant bit positions of the temporary result to generate the accumulate result.

Claim 12

A method as in claim 6, further comprising the steps of: a) filling less significant bits of the CHI register with ones; and b) if adding the shifted part of the C mantissa to the (A*B) mantissa generates a carry, incrementing the CHI register.

Claim 13

A method as in claim 10, further comprising the step of using any bits of C shifted out of the range of the (A*B) mantissa, and any bits shifted out of the temporary result, to round the merged result.