US5752015A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for repetitive execution of string instructions without branch or loop microinstructions
Assignee: IP First LLC
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Filing: 1996-03-29
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Granted: 1998-05-12
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Expires: 2016-03-29
Abstract
Abstract An apparatus and method for improving the execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation to be performed, and an execution unit for executing the micro instruction sequence. In addition, a counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from a counter which indicates that all of the string has been operated upon. In addition, the execution unit receives the signal from the counter and tests subsequent micro instructions to determine whether they are associated with string instructions. If so, the execution unit performs NOPs in place of those micro instructions.
Inventors
- 👤 Glenn Henry
- 👤 Terry Parks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 01:14
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
181 words
A processing system for executing instructions, including string instructions, within a computing environment, the processing system comprising: an instruction memory for storing said string instructions; data memory, for storing data upon which said string instructions operate: a translator connected to said instruction memory for receiving said string instructions from said instruction memory and for generating a sequence of micro instructions for each of said string instructions, an execution unit connected to said translator, for receiving said sequence of micro instructions from said translator and for executing said micro instructions; and a counter, connected to said translator and to said execution unit for storing a count value associated with the number of times said sequence of micro instructions is to be executed for each of said string instructions for counting said number of times said sequence of micro instructions is executed, and for providing a signal indicative that said counted number of times equals said stored number of times, wherein said sequence of micro instructions generated by said translator contain information indicating that said micro instructions are associated with said string instructions.
Claim 2
Dependent Claim
181 words
A processing system for executing instructions, including string instructions, within a computing environment, the processing system comprising: an instruction memory for storing said string instructions; data memory, for storing data upon which said string instructions operate: a translator connected to said instruction memory for receiving said string instructions from said instruction memory and for generating a sequence of micro instructions for each of said string instructions, an execution unit connected to said translator, for receiving said sequence of micro instructions from said translator and for executing said micro instructions; and a counter, connected to said translator and to said execution unit for storing a count value associated with the number of times said sequence of micro instructions is to be executed for each of said string instructions for counting said number of times said sequence of micro instructions is executed, and for providing a signal indicative that said counted number of times equals said stored number of times, wherein said sequence of micro instructions generated by said translator contain information indicating that said micro instructions are associated with said string instructions.
Claim 3
Dependent Claim
178 words
A processing system for executing instructions including string instructions, within a computing environment, the processing system comprising: an instruction memory, for storing said string instructions; data memory, for storing data upon which said string instructions operate; a translator, connected to said instruction memory, for receiving said string instructions from said instruction memory and for generating a sequence of micro instructions for each of said string instructions; an execution unit, connected to said translator, for receiving, said sequence of micro instructions from said translator, and for executing said micro instructions; and a counter, connected to said translator and to said execution unit, for storing a count value associated with the number of times said sequence of micro instructions is to be executed for each of said string instructions for counting said number of times said sequence of micro instructions is executed and for providing a signal indicative that said counted number of times equals said stored number of times, wherein said micro instructions comprise a control bit which indicates that said micro instructions are associated with said string instructions.
Claim 4
Dependent Claim
178 words
A processing system for executing instructions including string instructions, within a computing environment, the processing system comprising: an instruction memory, for storing said string instructions; data memory, for storing data upon which said string instructions operate; a translator, connected to said instruction memory, for receiving said string instructions from said instruction memory and for generating a sequence of micro instructions for each of said string instructions; an execution unit, connected to said translator, for receiving, said sequence of micro instructions from said translator, and for executing said micro instructions; and a counter, connected to said translator and to said execution unit, for storing a count value associated with the number of times said sequence of micro instructions is to be executed for each of said string instructions for counting said number of times said sequence of micro instructions is executed and for providing a signal indicative that said counted number of times equals said stored number of times, wherein said micro instructions comprise a control bit which indicates that said micro instructions are associated with said string instructions.
Claim 5
Dependent Claim
36 words
The processing system as recited in claim 1 wherein said execution unit further comprises string detection circuitry, connected to said translator, which detects whether micro instructions generated by said translator are associated with said string instructions.
Claim 6
Dependent Claim
49 words
The processing system as recited in claim 3 wherein said execution unit is connected to said signal provided by said counter, and wherein, upon receipt of said signal from said counter, does not execute subsequent micro instructions which are detected to be said micro instructions until said signal changes.
Claim 7
Dependent Claim
27 words
The processing system as recited in claim 4 wherein said execution unit turns said subsequent micro instructions associated with said string instructions into NOPs (no operation instructions).
Claim 8
Dependent Claim
168 words
A microprocessor for executing instructions, including macro string instructions the microprocessor comprising; an instruction cache, for storing instructions including said macro string instructions; a translator, connected to said instruction cache, for receiving said macro string instructions, and for translating each of said macro string instructions into a micro instruction sequence; a register file, connected to said translator, for storing addresses of data upon which said micro instruction sequence operates; an execution unit, connected to said translator and to said register file, for executing said micro instruction sequence; and a counter connected to said translator, and to said execution unit, for storing a count value associated with the number of times said micro instruction sequence is to be executed for counting said number of times said sequence is executed, and for providing a signal indicative that said counted number of times equals said stored number of times; wherein micro instructions within said sequence contain control information for indicating that said micro instructions are associated with said macro string instructions.
Claim 9
Dependent Claim
168 words
A microprocessor for executing instructions, including macro string instructions the microprocessor comprising; an instruction cache, for storing instructions including said macro string instructions; a translator, connected to said instruction cache, for receiving said macro string instructions, and for translating each of said macro string instructions into a micro instruction sequence; a register file, connected to said translator, for storing addresses of data upon which said micro instruction sequence operates; an execution unit, connected to said translator and to said register file, for executing said micro instruction sequence; and a counter connected to said translator, and to said execution unit, for storing a count value associated with the number of times said micro instruction sequence is to be executed for counting said number of times said sequence is executed, and for providing a signal indicative that said counted number of times equals said stored number of times; wherein micro instructions within said sequence contain control information for indicating that said micro instructions are associated with said macro string instructions.
Claim 10
Dependent Claim
35 words
The microprocessor as recited in claim 6 wherein said execution unit further comprises string detection circuitry for reading said control information, and for determining whether said micro instructions are associated with said macro string instructions.
Claim 11
Dependent Claim
51 words
The microprocessor as recited in claim 7 wherein said execution unit is connected to said indicative signal provided by said counter, and wherein, upon receipt of said signal from said counter, turns subsequent micro instructions associated with said macro string instructions into NOPs (no operation instructions) until said indicative signal changes.
Claim 12
Independent Claim
118 words
A method for executing a repetitive string instruction in a processing environment having a translator and an execution unit, the method comprising: translating the repetitive string instruction into a micro instruction sequence; storing a count value indicative of the number of times said micro instruction sequence is to be executed; repetitively generating said micro instruction sequence; executing said repetitively generated micro instruction sequence; counting the number of times said micro instruction sequence is executed; and when the counted number of times equals the stored number of times stopping execution of a subsequent repetitively generated micro instruction sequence, said stopping execution further comprising: detecting whether said subsequent repetitively generated micro instruction sequence is associated with said repetitive string instruction.
Claim 13
Independent Claim
118 words
A method for executing a repetitive string instruction in a processing environment having a translator and an execution unit, the method comprising: translating the repetitive string instruction into a micro instruction sequence; storing a count value indicative of the number of times said micro instruction sequence is to be executed; repetitively generating said micro instruction sequence; executing said repetitively generated micro instruction sequence; counting the number of times said micro instruction sequence is executed; and when the counted number of times equals the stored number of times stopping execution of a subsequent repetitively generated micro instruction sequence, said stopping execution further comprising: detecting whether said subsequent repetitively generated micro instruction sequence is associated with said repetitive string instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |