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US5751999A
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Processor and data memory for outputting and receiving data on different buses for storage in the same location
Assignee: Panasonic Holdings Corp
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Filing: 1995-06-20
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Granted: 1998-05-12
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Expires: 2015-06-20
Abstract
Abstract A digital signal processor includes a data memory which can be connected to, each of an M-bus, an A-bus, and a B-bus, each serving as a data bus, a pointer for supplying a data address to the data memory, and a decoder for supplying a control signal to the data memory such that one of a read cycle, a write cycle and a read/write cycle is selected in accordance with a result of decoding an instruction. When the read/write cycle has been selected, the data memory outputs data stored at a location designated by the data address from the pointer onto one of the buses, such as the M-bus, while receiving data from another bus, such as the A-bus, and storing the data thus received at the same location as designated by the data address. In one embodiment, the data memory includes a write circuit which has a latch circuit for temporarily holding data received from the data bus in a given memory cycle preceding the read/write cycle. Data is read from a given location in the data memory and another data is subsequently written at the same location in the read/write cycle. For example, two different data buses are used for reading data and writing data, respectively. Consequently, not only the read cycle and write cycle, but also the read/write cycle are enabled, which implements a data memory higher in performance than conventional ones without using a technique of increasing the speed of circuit operation.
Inventors
- 👤 Takao Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:27
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1684
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A processor comprising: a plurality of data buses; means for generating a data address; a cycle selecting means for selecting one of a read cycle, a write cycle, and a read/write cycle; and a data memory for outputting data stored at a location designated by said data address to any one of said plurality of data buses when the read cycle has been selected, receiving data from any one of said plurality of data buses and storing the data thus received at the location designated by said data address when the write cycle has been selected, and outputting the data stored at the location designated by said data address to any one of said plurality of data buses, while receiving data from another one of said plurality of data buses and storing the data thus received at the same location as designated by said data address, when the read/write cycle has been selected.
Claim 2
Dependent Claim
153 words
A processor comprising: a plurality of data buses; means for generating a data address; a cycle selecting means for selecting one of a read cycle, a write cycle, and a read/write cycle; and a data memory for outputting data stored at a location designated by said data address to any one of said plurality of data buses when the read cycle has been selected, receiving data from any one of said plurality of data buses and storing the data thus received at the location designated by said data address when the write cycle has been selected, and outputting the data stored at the location designated by said data address to any one of said plurality of data buses, while receiving data from another one of said plurality of data buses and storing the data thus received at the same location as designated by said data address, when the read/write cycle has been selected.
Claim 3
Dependent Claim
59 words
A processor according to claim 1, further comprising means for performing an operation with respect to data read onto a data bus from said data memory in a given read/write cycle and supplying data via another data bus to said data memory such that the data thus supplied is written in said data memory in the given read/write cycle.
Claim 4
Dependent Claim
85 words
A processor according to claim 1, wherein said cycle selecting means comprises: an instruction memory for storing a plurality of instructions therein: means for supplying an instruction address to said instruction memory so that one of the plurality of instructions is fetched from said instruction memory; and a decoder for decoding the fetched instruction, and for selecting one of the read cycle, the write cycle, and the read/write cycle in accordance with an instruction type of the fetched instruction that has been detected through decoding.
Claim 5
Dependent Claim
115 words
A processor according to claim 3, wherein said decoder further has a function of designating, in accordance with the instruction type of the fetched instruction that has been detected through decoding, one of said plurality of data buses to which said data memory will output data when the read cycle has been selected, one of said plurality of data buses from which said data memory will receive data when the write cycle has been selected, and one of said plurality of data buses to which said data memory will output data and another one of said plurality of data buses from which said data memory will receive data when the read/write cycle has been selected.
Claim 6
Dependent Claim
164 words
A processor according to claim 4, wherein said data memory comprises: a storing means for storing plural items of data therein; a read circuit for outputting data stored at a location designated by said data address in said storing means to the designated one of said plurality of data buses when one of the read cycle and the read/write cycle has been selected; and a write circuit for receiving data from the designated one of said plurality of data buses and storing the data thus received at the location designated by said data address in said storing means when the write cycle has been selected, and outputting the data stored at the location designated by said data address to the designated one of said plurality of data buses, while receiving data from another designated one of said plurality of data buses and storing the data thus received at the same location as designated by said data address, when the read/write cycle has been selected.
Claim 7
Dependent Claim
106 words
A single-port data memory for use in a processor having a data bus and means for generating a data address, said data memory comprising: a storing means for storing plural items of data therein; a read circuit for outputting, to said data bus, data stored at a location designated by said data address in said storing means in a read/write cycle; and a write circuit for temporarily holding data received from said data bus in a given memory cycle preceding said read/write cycle and storing the held data at the same location as designated by said data address in said storing means in said read/write cycle.
Claim 8
Dependent Claim
106 words
A single-port data memory for use in a processor having a data bus and means for generating a data address, said data memory comprising: a storing means for storing plural items of data therein; a read circuit for outputting, to said data bus, data stored at a location designated by said data address in said storing means in a read/write cycle; and a write circuit for temporarily holding data received from said data bus in a given memory cycle preceding said read/write cycle and storing the held data at the same location as designated by said data address in said storing means in said read/write cycle.
Claim 9
Dependent Claim
26 words
A single-port data memory according to claim 6, wherein said write circuit comprises a latch circuit for temporarily holding the data received from said data bus.
Claim 10
Dependent Claim
41 words
A single-port data memory according to claim 7, wherein said write circuit further comprises a selector for supplying, to said storing means, one of the data temporarily held by said latch circuit and the data received directly from said data bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |