US5751651A
Expired / Lapsed
US
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Semiconductor integrated circuit device having a hierarchical power source configuration
Assignee: Mitsubishi Electric Corp
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Filing: 1995-10-23
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Granted: 1998-05-12
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Expires: 2015-10-23
Abstract
Abstract A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in voltage between the sub source voltage transmission line and the main source voltage transmission line to operate at high speed with low current consumption.
Inventors
- 👤 Tsukasa Ooishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/408; G11C11/4085; G11C11/409; G11C11/4094; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G11C5/147; G11C7/06; G11C7/065; G11C8/00; G11C8/14; H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/0016
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
192 words
A semiconductor integrated circuit device comprising: a first main voltage transmission line for transmitting a voltage of a first logic level; a plurality of first sub voltage transmission lines; a plurality of first resistive elements connected between respective ones of said plurality of first sub voltage transmission lines and said first main voltage transmission line; a second main voltage transmission line for transmitting a voltage of a second logic level; a plurality of second sub voltage transmission lines respectively disposed corresponding to said plurality of first sub voltage transmission lines; a plurality of second resistive elements connected between respective ones of said plurality of second sub voltage transmission lines and said second main voltage transmission line; and a plurality of gate circuits divided into a plurality of groups corresponding to respective pairs of said plurality of first sub voltage transmission lines and said plurality of second sub voltage transmission lines, each of the gate circuits receiving voltages on corresponding first and second sub voltage transmission lines respectively as one operating source voltage and another operating source voltage, each the gate circuit performing a predetermined logic process on a received signal for outputting.
Claim 2
Dependent Claim
192 words
A semiconductor integrated circuit device comprising: a first main voltage transmission line for transmitting a voltage of a first logic level; a plurality of first sub voltage transmission lines; a plurality of first resistive elements connected between respective ones of said plurality of first sub voltage transmission lines and said first main voltage transmission line; a second main voltage transmission line for transmitting a voltage of a second logic level; a plurality of second sub voltage transmission lines respectively disposed corresponding to said plurality of first sub voltage transmission lines; a plurality of second resistive elements connected between respective ones of said plurality of second sub voltage transmission lines and said second main voltage transmission line; and a plurality of gate circuits divided into a plurality of groups corresponding to respective pairs of said plurality of first sub voltage transmission lines and said plurality of second sub voltage transmission lines, each of the gate circuits receiving voltages on corresponding first and second sub voltage transmission lines respectively as one operating source voltage and another operating source voltage, each the gate circuit performing a predetermined logic process on a received signal for outputting.
Claim 3
Dependent Claim
134 words
The semiconductor integrated circuit device as claimed in claim 1, further comprising: a plurality of first capacitors respectively provided corresponding to said plurality of first sub voltage transmission lines, each the first capacitor having one electrode node connected to a corresponding first sub voltage transmission line and another electrode node supplied with a voltage of the second logic level, said plurality of first capacitors respectively formed of insulated gate type field effect transistors; and a plurality of second capacitors respectively provided corresponding to said plurality of second sub voltage transmission lines, each the second capacitor having one electrode node connected to a corresponding second sub voltage transmission line and another electrode node supplied with a voltage of the first logic level, said plurality of second capacitors respectively comprising insulated gate type field effect transistors.
Claim 4
Dependent Claim
125 words
A semiconductor integrated circuit device comprising: a main voltage transmission line for transmitting a voltage of a first logic level; a plurality of sub voltage transmission lines; at least one resistive element connected between at least one ones of said plurality of sub voltage transmission lines and said main voltage transmission line; a plurality of gate circuits respectively divided into groups corresponding to said plurality of sub voltage transmission lines, each group of the gate circuits receiving voltage from the corresponding sub voltage transmission line as an operating source voltage, and performing a predetermined logic process on a received signal for outputting; and connection means for interconnecting said plurality of sub voltage transmission lines for a predetermined period in response to a power-on detection signal.
Claim 5
Dependent Claim
125 words
A semiconductor integrated circuit device comprising: a main voltage transmission line for transmitting a voltage of a first logic level; a plurality of sub voltage transmission lines; at least one resistive element connected between at least one ones of said plurality of sub voltage transmission lines and said main voltage transmission line; a plurality of gate circuits respectively divided into groups corresponding to said plurality of sub voltage transmission lines, each group of the gate circuits receiving voltage from the corresponding sub voltage transmission line as an operating source voltage, and performing a predetermined logic process on a received signal for outputting; and connection means for interconnecting said plurality of sub voltage transmission lines for a predetermined period in response to a power-on detection signal.
Claim 6
Dependent Claim
44 words
The semiconductor integrated circuit device as claimed in claim 3, wherein said connection means comprises means for interconnecting each of said plurality of sub voltage transmission lines and said main voltage transmission line for the predetermined period in response to the power-on detection signal.
Claim 7
Dependent Claim
55 words
The semiconductor integrated circuit device as claimed in claim 3, wherein said connection means comprises means for interconnecting said plurality of sub voltage transmission lines for a predetermined period and connecting at least one of said plurality of sub voltage transmission lines to said main voltage transmission line in response to the power-on detection signal.
Claim 8
Dependent Claim
60 words
The semiconductor integrated circuit device as claimed in claim 3, wherein said connection means comprises a switching transistor provided between each of said plurality of sub voltage transmission lines and said main voltage transmission line and rendered conductive upon activation of either one of the power-on detection signal and a group specification signal for specifying a sub voltage transmission line.
Claim 9
Dependent Claim
25 words
The semiconductor integrated circuit device as claimed in claim 3, wherein said main voltage transmission line transmits a voltage higher than the operating source voltage.
Claim 10
Dependent Claim
65 words
The semiconductor integrated circuit device as claimed in claim 7, further comprising: a source voltage transmission line for transmitting the operating source voltage; and means provided between each of said plurality of sub voltage transmission lines and said source voltage transmission line, for connecting each of said sub voltage transmission lines and said source voltage transmission line together upon inactivation of the power-on detection signal.
Claim 11
Dependent Claim
80 words
The semiconductor integrated circuit device as claimed in claim 3, further comprising: a plurality of switching transistors respectively provided corresponding to said plurality of sub voltage transmission lines, each of the switching transistors transmitting a voltage to a corresponding sub voltage transmission line for said predetermined period in response to the power-on detection signal, said voltage chancing in a common direction with a chance of a voltage on said main voltage transmission line at power-on of the integrated circuit device.
References Cited (Backward Citations)
US5583457A
Cited
US5521527A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |